US9508822B2ActiveUtilityPatentIndex 82
Semiconductor device
Est. expiryMar 28, 2033(~6.7 yrs left)· nominal 20-yr term from priority
H10D 64/693H10D 64/691H10D 64/513H10D 62/8503H10D 30/668H10D 30/603H10D 30/475H10D 30/63H10D 30/025H10D 30/021H10D 30/015H10D 64/685H01L 29/518H01L 29/513H01L 29/517H01L 29/2003H01L 29/7786H01L 29/7813H01L 29/7835H01L 29/4236
82
PatentIndex Score
13
Cited by
40
References
25
Claims
Abstract
A semiconductor device comprises: a gate insulating film 190 stacked on a semiconductor layer 130 ; and a gate electrode layer 230 stacked on the gate insulating film 190 and provided to apply a voltage via the gate insulating film 190 for formation of a channel in the semiconductor layer 130 . The gate insulating film 190 includes: a first insulation film 192 stacked on the semiconductor layer 130 ; and a second insulation film 194 between the first insulation film 192 and the gate electrode layer 230 . When ∈ 1 and ∈ 2 respectively represent relative permittivities of the first and second insulation film 192, 194 , d 1 [nm] and d 2 [nm] represent film thicknesses of the first and second insulation film 192, 194 , and Vmax [V] represents a rated voltage applicable to the gate electrode layer 230 , the semiconductor device is configured to satisfy ∈ 1<∈2 and meet (C1): V max d 1 + ɛ 1 ɛ 2 · d 2 ≦ 21 [ M V / cm ] . ( C1 )
Claims
exact text as granted — not AI-modifiedThe invention claimed is:
1. A semiconductor device, comprising:
a gate insulating film stacked on one surface of a semiconductor layer; and
a gate electrode layer stacked on the gate insulating film and provided to apply a voltage via the gate insulating film for formation of a channel in the semiconductor layer,
wherein the gate insulating film includes:
a first insulation film stacked on one surface of the semiconductor layer; and
a second insulation film placed between the first insulation film and the gate electrode layer,
wherein when ∈ 1 and ∈ 2 respectively represent relative permittivities of the first insulation film and the second insulation film, d 1 [nm] and d 2 [nm] represent film thicknesses of the first insulation film and the second insulation film, and Vmax [V] represents a rated voltage applicable to the gate electrode layer, the gate insulating film is configured to satisfy ∈ 1 <∈ 2 and meet Math Expression (C1):
V
max
d
1
+
ɛ1
ɛ2
·
d
2
≦
21
[
MV
/
cm
]
,
(
C1
)
wherein the film thickness d 1 of the first insulation film is equal to or greater than 10 nm, and the film thickness d 2 of the second insulation film is greater than d 1 ,
wherein the semiconductor layer includes a plurality of semiconductor layers comprising:
a first conductivity-type semiconductor layer formed on a substrate, and including a doped GaN layer;
a second conductivity-type semiconductor layer formed on the first conductivity-type semiconductor layer; and
an other first conductivity-type semiconductor layer formed on the second conductivity-type semiconductor layer, and
wherein the gate insulating film is formed in a trench formed in the plurality of semiconductor layers, a bottom of the trench being formed in the doped GaN layer of the first conductivity-type semiconductor layer.
2. The semiconductor device according to claim 1 , wherein the gate insulating film meets Math Expression (C2):
V
max
d
1
+
ɛ1
ɛ2
·
d
2
≦
16
[
MV
/
cm
]
.
(
C2
)
3. The semiconductor device according to claim 1 , wherein when a dielectric breakdown field intensity of the first insulation film is E 1 bd [MV/cm], the gate insulating film meets Math Expression (C3):
ɛ1
·
E
1
bd
V
max
≦
1
d
1
ɛ1
+
d
2
ɛ2
.
(
C3
)
4. The semiconductor device according to claim 3 , wherein the dielectric breakdown field intensity E 1 bd is 10 MV/cm.
5. The semiconductor device according to claim 1 , wherein the rated voltage Vmax is equal to or greater than 10 V.
6. The semiconductor device according to claim 1 , wherein the first insulation film comprises an insulating material mainly including Si, and the second insulation film comprises an insulating material including an oxide or an oxynitride containing one or more species selected among Hf, Zr and Al.
7. The semiconductor device according to claim 1 , wherein the first insulation film comprises an insulating material mainly including Al, and the second insulation film comprises an insulating material including an oxide or an oxynitride containing one or more species selected among Hf and Zr.
8. The semiconductor device according to claim 1 , wherein the second insulation film is structured by stacking a plurality of layers.
9. The semiconductor device according to claim 1 , wherein the semiconductor layer includes a group III nitride semiconductor.
10. The semiconductor device of claim 1 , further comprising:
a plurality of semiconductor layers including the semiconductor layer; and
a trench formed in the plurality of semiconductor layers,
wherein the gate insulating film is formed in the trench and the gate electrode layer is formed on the gate insulating film in the trench.
11. The semiconductor device of claim 1 , wherein the first insulating film comprises one of aluminum oxide (Al 2 O 3 ) and aluminum oxynitride (AlON).
12. A semiconductor device comprising:
a substrate;
a plurality of semiconductor layers formed on the substrate;
a trench formed in the plurality of semiconductor layers;
a gate insulating film formed in the trench, the gate insulating film comprising:
a first insulation film formed in trench and having a film thickness d 1 equal to or greater than 10 nm; and
a second insulation film formed on the first insulation film and having a film thickness d 2 greater than d 1 ; and
a gate electrode formed in the trench on the gate insulating film,
wherein the gate insulating film is configured to satisfy ∈ 1 <∈ 2 and meet Math Expression (C1):
V
max
d
1
+
ɛ1
ɛ2
·
d
2
≦
21
[
MV
/
cm
]
,
(
C1
)
where ∈ 1 and ∈ 2 respectively represent relative permittivities of the first insulation film and the second insulation film, d 1 [nm] and d 2 [nm] represent film thicknesses of the first insulation film and the second insulation film, and Vmax [V] represents a rated voltage applicable to the gate electrode layer,
wherein the plurality of semiconductor layers comprises:
a first conductivity-type semiconductor layer formed on the substrate, and including a doped GaN layer;
a second conductivity-type semiconductor layer formed on the first conductivity-type semiconductor layer; and
an other first conductivity-type semiconductor layer formed on the second conductivity-type semiconductor layer, and
wherein a bottom of the trench is formed in the doped GaN layer of the first conductivity-type semiconductor layer.
13. The semiconductor device of claim 12 , wherein the first insulation film is formed on a bottom surface of the trench and a side surface of the trench, and on an upper surface of the other first conductivity-type semiconductor layer.
14. The semiconductor device of claim 12 , wherein a bottom of the gate electrode is formed at a height which is less than a height of a surface of the first conductivity-type semiconductor layer.
15. The semiconductor device of claim 12 , further comprising:
a source electrode penetrating the gate insulating film and contacting the other first conductivity-type semiconductor layer; and
a drain electrode formed on a surface of the substrate which is opposite the plurality of semiconductor layers.
16. The semiconductor device of claim 12 , further comprising:
an electrode penetrating the gate insulating film and the other first conductivity-type semiconductor layer, and contacting the second conductivity-type semiconductor layer.
17. The semiconductor device of claim 12 , wherein the plurality of semiconductor layers comprises a plurality of GaN semiconductor layers.
18. A semiconductor device, comprising:
a gate insulating film stacked on one surface of a semiconductor layer; and
a gate electrode layer stacked on the gate insulating film and provided to apply a voltage via the gate insulating film for formation of a channel in the semiconductor layer,
wherein the gate insulating film includes:
a first insulation film stacked on one surface of the semiconductor layer; and
a second insulation film placed between the first insulation film and the gate electrode layer,
wherein when ∈ 1 and ∈ 2 respectively represent relative permittivities of the first insulation film and the second insulation film, d 1 [nm] and d 2 [nm] represent film thicknesses of the first insulation film and the second insulation film, and Vmax [V] represents a rated voltage applicable to the gate electrode layer, the gate insulating film is configured to satisfy ∈ 1 <∈ 2 and meet Math Expression (C1):
V
max
d
1
+
ɛ1
ɛ2
·
d
2
≦
21
[
MV
/
cm
]
(
C1
)
wherein the film thickness d 1 of the first insulation film is equal to or greater than 10 nm, and the film thickness d 2 of the second insulation film is greater than d 1 ,
wherein the semiconductor layer includes a plurality of semiconductor layers comprising:
a first conductivity-type semiconductor layer formed on a substrate, and including a doped GaN layer;
a second conductivity-type semiconductor layer formed on the first conductivity-type semiconductor layer; and
an other first conductivity-type semiconductor layer formed on the second conductivity-type semiconductor layer, the other first conductivity-type semiconductor layer being N-type semiconductor layer,
wherein the gate insulating film is formed in a trench formed in the plurality of semiconductor layers, a bottom of the trench being formed in the doped GaN layer of the first conductivity-type semiconductor layer, and
wherein the first conductivity-type semiconductor layer comprises an N-type semiconductor layer and the second conductivity-type semiconductor layer comprises a P-type semiconductor layer.
19. The semiconductor device according to claim 18 , wherein when a dielectric breakdown field intensity of the first insulation film is E 1 bd [MV/cm], the gate insulating film meets Math Expression (C3):
ɛ1
·
E
1
bd
V
max
≦
1
d
1
ɛ1
+
d
2
ɛ2
.
(
C3
)
20. A semiconductor device comprising:
a substrate;
a plurality of semiconductor layers formed on the substrate;
a trench formed in the plurality of semiconductor layers;
a gate insulating film formed in the trench, the gate insulating film comprising:
a first insulation film formed in trench and having a film thickness d 1 equal to or greater than 10 nm; and
a second insulation film formed on the first insulation film, and having a film thickness d 2 greater than d 1 ; and
a gate electrode formed in the trench on the gate insulating film,
wherein the gate insulating film is configured to satisfy ∈ 1 <∈2 and meet Math Expression (C1):
V
max
d
1
+
ɛ1
ɛ2
·
d
2
≦
21
[
MV
/
cm
]
,
(
C1
)
where ∈ 1 and ∈ 2 respectively represent relative permittivities of the first insulation film and the second insulation film, d 1 [nm] and d 2 [nm] represent film thicknesses of the first insulation film and the second insulation film, and Vmax [V] represents a rated voltage applicable to the gate electrode layer,
wherein the plurality of semiconductor layers comprises:
a first conductivity-type semiconductor layer formed on the substrate, the first conductivity-type semiconductor layer being N-type semiconductor layer and including a doped GaN layer;
a second conductivity-type semiconductor layer formed on the first conductivity-type semiconductor layer, the second conductivity-type semiconductor layer being P-type semiconductor layer; and
an other first conductivity-type semiconductor layer formed on the second conductivity-type semiconductor layer, the other first conductivity-type semiconductor layer being N-type semiconductor layer, and
wherein a bottom of the trench is formed in the doped GaN layer of the first conductivity-type semiconductor layer.
21. The semiconductor device according to claim 20 , wherein when a dielectric breakdown field intensity of the first insulation film is E 1 bd [MV/cm], the gate insulating film meets Math Expression (C3):
ɛ1
·
E
1
bd
V
max
≦
1
d
1
ɛ1
+
d
2
ɛ2
.
(
C3
)
22. A semiconductor device, comprising:
a gate insulating film stacked on one surface of a semiconductor layer; and
a gate electrode layer stacked on the gate insulating film and provided to apply a voltage via the gate insulating film for formation of a channel in the semiconductor layer,
wherein the gate insulating film includes:
a first insulation film stacked on one surface of the semiconductor layer; and
a second insulation film placed between the first insulation film and the gate electrode layer,
wherein when ∈ 1 and ∈ 2 respectively represent relative permittivities of the first insulation film and the second insulation film, d 1 [nm] and d 2 [nm] represent film thicknesses of the first insulation film and the second insulation film, and Vmax [V] represents a rated voltage applicable to the gate electrode layer, the gate insulating film is configured to satisfy ∈ 1 <∈ 2 and meet Math Expression (C1):
V
max
d
1
+
ɛ1
ɛ2
·
d
2
≦
21
[
MV
/
cm
]
,
(
C1
)
wherein the first insulation film comprises an insulating material mainly including Al, and the film thickness d 1 of the first insulation film is equal to or greater than 10 nm,
wherein the semiconductor layer includes a plurality of semiconductor layers comprising:
a first conductivity-type semiconductor layer formed on the substrate, and including a doped GaN layer;
a second conductivity-type semiconductor layer formed on the first conductivity-type semiconductor layer; and
an other first conductivity-type semiconductor layer formed on the second conductivity-type semiconductor layer, and
wherein the gate insulating film is formed in a trench formed in the plurality of semiconductor layers, a bottom of the trench being formed in the doped GaN layer of the first conductivity-type semiconductor layer.
23. A semiconductor device comprising:
a substrate;
a plurality of semiconductor layers formed on the substrate;
a trench formed in the plurality of semiconductor layers;
a gate insulating film formed in the trench, the gate insulating film comprising:
a first insulation film formed in trench and having a film thickness d 1 equal to or greater than 10 nm, and comprising an insulating material mainly including Al; and
a second insulation film formed on the first insulation film; and
a gate electrode formed in the trench on the gate insulating film,
wherein the gate insulating film is configured to satisfy ∈ 1 <∈ 2 and meet Math Expression (C1):
V
max
d
1
+
ɛ1
ɛ2
·
d
2
≦
21
[
MV
/
cm
]
,
(
C1
)
where ∈ 1 and ∈ 2 respectively represent relative permittivities of the first insulation film and the second insulation film, d 1 [nm] and d 2 [nm] represent film thicknesses of the first insulation film and the second insulation film, and Vmax [V] represents a rated voltage applicable to the gate electrode layer,
wherein the plurality of semiconductor layers comprises:
a first conductivity-type semiconductor layer formed on the substrate, and including a doped GaN layer;
a second conductivity-type semiconductor layer formed on the first conductivity-type semiconductor layer; and
an other first conductivity-type semiconductor layer formed on the second conductivity-type semiconductor layer, and
wherein a bottom of the trench is formed in the doped GaN layer of the first conductivity-type semiconductor layer.
24. A semiconductor device, comprising:
a gate insulating film stacked on one surface of a semiconductor layer; and
a gate electrode layer stacked on the gate insulating film and provided to apply a voltage via the gate insulating film for formation of a channel in the semiconductor layer,
wherein the gate insulating film includes:
a first insulation film stacked on one surface of the semiconductor layer; and
a second insulation film placed between the first insulation film and the gate electrode layer,
wherein when ∈ 1 and ∈ 2 respectively represent relative permittivities of the first insulation film and the second insulation film, d 1 [nm] and d 2 [nm] represent film thicknesses of the first insulation film and the second insulation film, and Vmax [V] represents a rated voltage applicable to the gate electrode layer, the gate insulating film is configured to satisfy ∈ 1 <∈ 2 and meet Math Expression (C1):
V
max
d
1
+
ɛ1
ɛ2
·
d
2
≦
21
[
MV
/
cm
]
(
C1
)
wherein the first insulation film comprises an insulating material mainly including Al, and the film thickness d 1 of the first insulation film is equal to or greater than 10 nm,
wherein the semiconductor layer includes a plurality of semiconductor layers comprising:
a first conductivity-type semiconductor layer formed on the substrate, and including a doped GaN layer;
a second conductivity-type semiconductor layer formed on the first conductivity-type semiconductor layer; and
an other first conductivity-type semiconductor layer formed on the second conductivity-type semiconductor layer, the other first conductivity-type semiconductor layer being N-type semiconductor layer,
wherein the gate insulating film is formed in a trench formed in the plurality of semiconductor layers, a bottom of the trench being formed in the doped GaN layer of the first conductivity-type semiconductor layer, and
wherein the first conductivity-type semiconductor layer comprises an N-type semiconductor layer and the second conductivity-type semiconductor layer comprises a P-type semiconductor layer.
25. A semiconductor device comprising:
a substrate;
a plurality of semiconductor layers formed on the substrate;
a trench formed in the plurality of semiconductor layers;
a gate insulating film formed in the trench, the gate insulating film comprising:
a first insulation film formed in trench and having a film thickness d 1 equal to or greater than 10 nm, and comprising an insulating material mainly including Al; and
a second insulation film formed on the first insulation film; and
a gate electrode formed in the trench on the gate insulating film,
wherein the gate insulating film is configured to satisfy ∈ 1 <∈ 2 and meet Math Expression (C1):
V
max
d
1
+
ɛ1
ɛ2
·
d
2
≦
21
[
MV
/
cm
]
,
(
C1
)
where ∈ 1 and ∈ 2 respectively represent relative permittivities of the first insulation film and the second insulation film, d 1 [nm] and d 2 [nm] represent film thicknesses of the first insulation film and the second insulation film, and Vmax [V] represents a rated voltage applicable to the gate electrode layer,
wherein the plurality of semiconductor layers comprises:
a first conductivity-type semiconductor layer formed on the substrate, the first conductivity-type semiconductor layer being N-type semiconductor layer and including a doped GaN layer;
a second conductivity-type semiconductor layer formed on the first conductivity-type semiconductor layer, the second conductivity-type semiconductor layer being P-type semiconductor layer; and
an other first conductivity-type semiconductor layer formed on the second conductivity-type semiconductor layer, the other first conductivity-type semiconductor layer being N-type semiconductor layer, and
wherein a bottom of the trench is formed in the doped GaN layer of the first conductivity-type semiconductor layer.Cited by (0)
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