Method for determining an optimal voltage pulse for programming a flash memory cell

Abstract

A method for determining an optimal voltage pulse for programming a flash memory cell, the optimal voltage pulse being defined by a voltage ramp from a non-zero initial voltage level during a programming duration, wherein the method takes into account a set of parameters including a programming window target value and a drain current target value of the memory cell.

The invention is claimed is: 
     
       1. A method for determining an optimal voltage pulse for programming a NOR-type flash memory cell comprising a floating gate, a control gate and a drain, said optimal voltage pulse, to be applied to the control gate of the memory cell, being defined by a voltage ramp from a non-zero initial voltage level during a programming duration, the method comprising:
 providing a set of parameters including a programming window target value and a drain current target value of the memory cell; 
 dynamically measuring a drain current of the memory cell when a rectangular-shaped voltage pulse is applied to the control gate; 
 providing a transistor equivalent to the memory cell and comprising a gate electrode and a drain electrode, such that the a drain current of the transistor is equal to the drain current of the memory cell when the gate electrode of the transistor is brought to a potential equal to the a potential of the floating gate of the memory cell; 
 dynamically measuring the drain current of the transistor as a function of the potential of the gate electrode of the transistor; 
 determining the potential of the floating gate during the rectangular-shaped voltage pulse, from the measurement of the drain current of the memory cell and the measurement of the drain current of the transistor; 
 determining, respectively from the drain current target value, the potential of the floating gate during the rectangular-shaped voltage pulse and from the programming window target value, the initial voltage level, a slope of the voltage ramp and the programming duration, such that the drain current of the memory cell during the optimal voltage pulse is substantially equal to the drain current target value; 
 and wherein the drain of the memory cell is brought, during the measurement of the drain current of the memory cell, to a constant potential identical to that of the drain electrode of the transistor during the measurement of the drain current of the transistor. 
 
     
     
       2. The method according to  claim 1 , wherein the initial voltage level is determined from the measurement of the drain current of the memory cell at a start of the rectangular-shaped voltage pulse, by measuring the value of the potential applied to the control gate of the memory cell for which the drain current is equal to the drain current target value of the memory cell. 
     
     
       3. The method according to  claim 1 , wherein the slope of the voltage ramp is determined from the derivative of the potential of the floating gate, when the potential of the floating gate reaches a floating gate potential target value corresponding to the drain current target value. 
     
     
       4. The method according to  claim 1 , wherein the programming duration is determined from the programming window target value and from the slope of the voltage ramp. 
     
     
       5. The method according to  claim 4 , wherein the programming duration is calculated using the following relationship:
     t   pulse =PW TG /S 
 where PW TG  is the programming window target value and S is the slope of the voltage ramp. 
 
     
     
       6. The method according to  claim 1 , wherein the transistor equivalent to the memory cell to program is comprised of a test flash memory cell, of identical geometry to the flash memory cell to program, having a floating gate and a control gate in short-circuit. 
     
     
       7. A non-transitory computer program product comprising instructions for implementing a method according to  claim 1 , when executed by a computer.