P
US9640476B2ActiveUtilityPatentIndex 41

Driving circuit and pin output order arranging method

Assignee: RAYDIUM SEMICONDUCTOR CORPPriority: Sep 15, 2015Filed: Jul 25, 2016Granted: May 2, 2017
Est. expirySep 15, 2035(~9.2 yrs left)· nominal 20-yr term from priority
Inventors:LO SHIN-TAILIN CHENG-NANHUNG SHAO-PING
H01L 23/50H01L 27/0207H10D 89/10H03K 19/1732
41
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42
Claims

Abstract

A driving circuit and a pin output order arranging method are disclosed. The driving circuit includes (M*N) pins and an arranging module. A first pin˜an N-th pin of the (M*N) pins, a (N+1)-th pin˜an 2N-th pin of the (M*N) pins, . . . , a [(M−1)*N+1]-th pin˜a (M*N)-th pin of the (M*N) pins are arranged along a first direction in a specific distance spaced to form a first row of pins˜an M-th row of pins. The first row of pins˜the M-th row of pins are staggered along a second direction in a staggering way or an aligning way. M and N are integers larger than 1. The arranging module correspondingly arranges the pin output order of the (M*N) pins according to different application modes of the driving circuit.

Claims

exact text as granted — not AI-modified
The invention claimed is: 
     
       1. A driving circuit having a pin output order arranging function, the driving circuit comprising:
 (M*N) pins comprising a first pin, a second pin, . . . , and a (M*N)-th pin, wherein the first pin, the second pin, . . . , and an N-th pin of the (M*N) pins are arranged along a first direction in a specific distance spaced to form a first row of pins, a (N+1)-th pin, a (N+2)-th pin, . . . , and an 2N-th pin of the (M*N) pins are arranged along the first direction in the specific distance spaced to form a second row of pins, . . . , and a [(M−1)*N+1]-th pin, a [(M−1)*N+2]-th pin, . . . , and a (M*N)-th pin of the (M*N) pins are arranged along the first direction in the specific distance spaced to form a M-th row of pins; the first row of pins, the second row of pins, . . . , and the M-th row of pins are staggered along a second direction in a staggering way or an aligning way, and M and N are integers larger than 1; and 
 an arranging module, coupled to the (M*N) pins, the arranging module correspondingly arranging a pin output order S1˜SMN of the (M*N) pins according to different application modes of the driving circuit. 
 
     
     
       2. The driving circuit of  claim 1 , wherein M=4, when an application mode of the driving circuit is a chip-on-glass (COG) mode, the pin output order S1˜S4N of the (4*N) pins arranged by the arranging module is: (S1) the first pin, (S2) the (2N+1)-th pin, (S3) the (N+1)-th pin, (S4) the (3N+1)-th pin, . . . , (S4N−3) the N-th pin, (S4N−2) the 3N-th pin, (S4N−1) the 2N-th pin, and (S4N) the 4N-th pin, so that a distance between two pins having adjacent output order corresponds to the COG mode. 
     
     
       3. The driving circuit of  claim 1 , wherein M=4, when an application mode of the driving circuit is a COG mode, the pin output order S1˜S4N of the (4*N) pins arranged by the arranging module is: (S1) the 4N-th pin, (S2) the 2N-th pin, (S3) the 3N-th pin, (S4) the N-th pin, . . . , (S4N−3) the (3N+1)-th pin, (S4N−2) the (N+1)-th pin, (S4N−1) the (2N+1)-th pin, and (S4N) the first pin, so that a distance between two pins having adjacent output order corresponds to the COG mode. 
     
     
       4. The driving circuit of  claim 1 , wherein M=4, when an application mode of the driving circuit is a chip-on-film (COF) mode, the pin output order S1˜S4N of the (4*N) pins arranged by the arranging module is: (S1) the (3N+K)-th pin in the fourth row of pins, (S2) the (2N+K)-th pin in the third row of pins, (S3) the (3N+K−1)-th pin in the fourth row of pins, (S4) the (2N+K−1)-th pin in the third row of pins, . . . , the (3N+1)-th pin in the fourth row of pins, the (2N+1)-th pin in the third row of pins, the first pin in the first row of pins, the (N+1)-th pin in the second row of pins, . . . , the N-th pin in the first row of pins, the 2N-th pin in the second row of pins, the 4N-th pin in the fourth row of pins, the 3N-th pin in the third row of pins, . . . , (S4N−1) the (3N+K+1)-th pin in the fourth row of pins, and (S4N) the (2N+K+1)-th pin in the third row of pins, K is a positive integer and 1≦K≦N, so that a distance between two pins having adjacent output order corresponds to the COF mode. 
     
     
       5. The driving circuit of  claim 1 , wherein M=4, when an application mode of the driving circuit is a COF mode, the pin output order S1˜S4N of the (4*N) pins arranged by the arranging module is: (S1) the K-th pin in the first row of pins, (S2) the (N+K)-th pin in the second row of pins, (S3) the (K+1)-th pin in the first row of pins, (S4) the (N+K+1)-th pin in the second row of pins, . . . , the 4N-th pin in the fourth row of pins, the 3N-th pin in the third row of pins, . . . , the (3N+1)-th pin in the fourth row of pins, the (2N+1)-th pin in the third row of pins, the first pin in the first row of pins, the (N+1)-th pin in the second row of pins, . . . , (S4N−1) the (K−1)-th pin in the first row of pins, and (S4N) the (N+K−1)-th pin in the second row of pins, K is a positive integer and 1≦K≦N, so that a distance between two pins having adjacent output order corresponds to the COF mode. 
     
     
       6. The driving circuit of  claim 1 , wherein M=4, when the first row of pins, the second row of pins, . . . , and the M-th row of pins are staggered in a first staggering way, a distance between the first pin in the first row of pins and the (2N+1)-th pin in the third row of pins along the first direction<a distance between the first pin in the first row of pins and the (N+1)-th pin in the second row of pins along the first direction<a distance between the first pin in the first row of pins and the (3N+1)-th pin in the fourth row of pins along the first direction. 
     
     
       7. The driving circuit of  claim 1 , wherein M=4, when an application mode of the driving circuit is a COG mode, the pin output order S1˜S4N of the (4*N) pins arranged by the arranging module is: (S1) the first pin, (S2) the (N+1)-th pin, (S3) the (2N+1)-th pin, (S4) the (3N+1)-th pin, . . . , (S4N−3) the N-th pin, (S4N−2) the 2N-th pin, (S4N−1) the 3N-th pin, and (S4N) the 4N-th pin, so that a distance between two pins having adjacent output order corresponds to the COG mode. 
     
     
       8. The driving circuit of  claim 1 , wherein M=4, when an application mode of the driving circuit is a COG mode, the pin output order S1˜S4N of the (4*N) pins arranged by the arranging module is: (S1) the 4N-th pin, (S2) the 3N-th pin, (S3) the 2N-th pin, (S4) the N-th pin, . . . , (S4N−3) the (3N+1)-th pin, (S4N−2) the (2N+1)-th pin, (S4N−1) the (N+1)-th pin, and (S4N) the first pin, so that a distance between two pins having adjacent output order corresponds to the COG mode. 
     
     
       9. The driving circuit of  claim 1 , wherein M=4, when an application mode of the driving circuit is a COF mode, the pin output order S1˜S4N of the (4*N) pins arranged by the arranging module is: (S1) the (3N+K)-th pin in the fourth row of pins, (S2) the (2N+K)-th pin in the third row of pins, (S3) the (3N+K−1)-th pin in the fourth row of pins, (S4) the (2N+K−1)-th pin in the third row of pins, . . . , the (3N+1)-th pin in the fourth row of pins, the (2N+1)-th pin in the third row of pins, the first pin in the first row of pins, the (N+1)-th pin in the second row of pins, . . . , the N-th pin in the first row of pins, the 2N-th pin in the second row of pins, the 4N-th pin in the fourth row of pins, the 3N-th pin in the third row of pins, . . . , (S4N−1) the (3N+K+1)-th pin in the fourth row of pins, and (S4N) the (2N+K+1)-th pin in the third row of pins, K is a positive integer and 1≦K≦N, so that a distance between two pins having adjacent output order corresponds to the COF mode. 
     
     
       10. The driving circuit of  claim 1 , wherein M=4, when an application mode of the driving circuit is a COF mode, the pin output order S1˜S4N of the (4*N) pins arranged by the arranging module is: (S1) the K-th pin in the first row of pins, (S2) the (N+K)-th pin in the second row of pins, (S3) the (K+1)-th pin in the first row of pins, (S4) the (N+K+1)-th pin in the second row of pins, . . . , the N-th pin in the first row of pins, the 2N-th pin in the second row of pins, the 4N-th pin in the fourth row of pins, the 3N-th pin in the third row of pins, . . . , the (3N+1)-th pin in the fourth row of pins, the (2N+1)-th pin in the third row of pins, the first pin in the first row of pins, the (N+1)-th pin in the second row of pins, . . . , (S4N−1) the (K−1)-th pin in the first row of pins, and (S4N) the (N+K−1)-th pin in the second row of pins, K is a positive integer and 1≦K≦N, so that a distance between two pins having adjacent output order corresponds to the COF mode. 
     
     
       11. The driving circuit of  claim 1 , wherein M=4, when the first row of pins, the second row of pins, . . . , and the M-th row of pins are staggered in a second staggering way, a distance between the first pin in the first row of pins and the (N+1)-th pin in the second row of pins along the first direction<a distance between the first pin in the first row of pins and the (2N+1)-th pin in the third row of pins along the first direction<a distance between the first pin in the first row of pins and the (3N+1)-th pin in the fourth row of pins along the first direction. 
     
     
       12. The driving circuit of  claim 1 , wherein M=4, when an application mode of the driving circuit is a COG mode, the pin output order S1˜S4N of the (4*N) pins arranged by the arranging module is: (S1) the first pin, (S2) the (3N+1)-th pin, (S3) the (N+1)-th pin, (S4) the (2N+1)-th pin, . . . , (S4N−3) the N-th pin, (S4N−2) the 4N-th pin, (S4N−1) the 2N-th pin, and (S4N) the 3N-th pin, so that a distance between two pins having adjacent output order corresponds to the COG mode. 
     
     
       13. The driving circuit of  claim 1 , wherein M=4, when an application mode of the driving circuit is a COG mode, the pin output order S1˜S4N of the (4*N) pins arranged by the arranging module is: (S1) the 3N-th pin, (S2) the 2N-th pin, (S3) the 4N-th pin, (S4) the N-th pin, . . . , (S4N−3) the (2N+1)-th pin, (S4N−2) the (N+1)-th pin, (S4N−1) the (3N+1)-th pin, and (S4N) the first pin, so that a distance between two pins having adjacent output order corresponds to the COG mode. 
     
     
       14. The driving circuit of  claim 1 , wherein M=4, when an application mode of the driving circuit is a COF mode, the pin output order S1˜S4N of the (4*N) pins arranged by the arranging module is: (S1) the (2N+K)-th pin in the third row of pins, (S2) the (3N+K)-th pin in the fourth row of pins, (S3) the (2N+K−1)-th pin in the third row of pins, (S4) the (3N+K−1)-th pin in the fourth row of pins, . . . , the (2N+1)-th pin in the third row of pins, the first pin in the first row of pins, the (N+1)-th pin in the second row of pins, . . . , the N-th pin in the first row of pins, the 2N-th pin in the second row of pins, the 3N-th pin in the third row of pins, the 4N-th pin in the fourth row of pins, . . . , (S4N−1) the (2N+K+1)-th pin in the third row of pins, and (S4N) the (3N+K+1)-th pin in the fourth row of pins, K is a positive integer and 1≦K≦N, so that a distance between two pins having adjacent output order corresponds to the COF mode. 
     
     
       15. The driving circuit of  claim 1 , wherein M=4, when an application mode of the driving circuit is a COF mode, the pin output order S1˜S4N of the (4*N) pins arranged by the arranging module is: (S1) the K-th pin in the first row of pins, (S2) the (N+K)-th pin in the second row of pins, (S3) the (K+1)-th pin in the first row of pins, (S4) the (N+K+1)-th pin in the second row of pins, . . . , the N-th pin in the first row of pins, the 2N-th pin in the second row of pins, the 3N-th pin in the third row of pins, the 4N-th pin in the fourth row of pins, . . . , the (2N+1)-th pin in the third row of pins, the (3N+1)-th pin in the fourth row of pins, the first pin in the first row of pins, the (N+1)-th pin in the second row of pins, . . . , (S4N−1) the (K−1)-th pin in the first row of pins, and (S4N) the (N+K−1)-th pin in the second row of pins, K is a positive integer and 1≦K≦N, so that a distance between two pins having adjacent output order corresponds to the COF mode. 
     
     
       16. The driving circuit of  claim 1 , wherein M=4, when the first row of pins, the second row of pins, . . . , and the M-th row of pins are staggered in a third staggering way, a distance between the first pin in the first row of pins and the (3N+1)-th pin in the fourth row of pins along the first direction<a distance between the first pin in the first row of pins and the (N+1)-th pin in the second row of pins along the first direction<a distance between the first pin in the first row of pins and the (2N+1)-th pin in the third row of pins along the first direction. 
     
     
       17. The driving circuit of  claim 1 , wherein M=4, when an application mode of the driving circuit is a COG mode, the pin output order S1˜S4N of the (4*N) pins arranged by the arranging module is: (S1) the first pin, (S2) the (N+1)-th pin, (S3) the (2N+1)-th pin, (S4) the (3N+1)-th pin, . . . , (S4N−3) the N-th pin, (S4N−2) the 2N-th pin, (S4N−1) the 3N-th pin, and (S4N) the 4N-th pin, so that a distance between two pins having adjacent output order corresponds to the COG mode. 
     
     
       18. The driving circuit of  claim 1 , wherein M=4, when an application mode of the driving circuit is a COG mode, the pin output order S1˜S4N of the (4*N) pins arranged by the arranging module is: (S1) the 4N-th pin, (S2) the 3N-th pin, (S3) the 2N-th pin, (S4) the N-th pin, . . . , (S4N−3) the (3N+1)-th pin, (S4N−2) the (2N+1)-th pin, (S4N−1) the (N+1)-th pin, and (S4N) the first pin, so that a distance between two pins having adjacent output order corresponds to the COG mode. 
     
     
       19. The driving circuit of  claim 1 , wherein M=4, when an application mode of the driving circuit is a COF mode, the pin output order S1˜S4N of the (4*N) pins arranged by the arranging module is: (S1) the (2N+K)-th pin in the third row of pins, (S2) the (3N+K)-th pin in the fourth row of pins, (S3) the (2N+K−1)-th pin in the third row of pins, (S4) the (3N+K−1)-th pin in the fourth row of pins, . . . , the (2N+1)-th pin in the third row of pins, the (3N+1)-th pin in the fourth row of pins, the first pin in the first row of pins, the (N+1)-th pin in the second row of pins, . . . , the N-th pin in the first row of pins, the 2N-th pin in the second row of pins, the 3N-th pin in the third row of pins, the 4N-th pin in the fourth row of pins, . . . , (S4N−1) the (2N+K+1)-th pin in the third row of pins, and (S4N) the (3N+K+1)-th pin in the fourth row of pins, K is a positive integer and 1≦K≦N, so that a distance between two pins having adjacent output order corresponds to the COF mode. 
     
     
       20. The driving circuit of  claim 1 , wherein M=4, when an application mode of the driving circuit is a COF mode, the pin output order S1˜S4N of the (4*N) pins arranged by the arranging module is: (S1) the K-th pin in the first row of pins, (S2) the (N+K)-th pin in the second row of pins, (S3) the (K+1)-th pin in the first row of pins, (S4) the (N+K+1)-th pin in the second row of pins, . . . , the N-th pin in the first row of pins, the 2N-th pin in the second row of pins, the 3N-th pin in the third row of pins, the 4N-th pin in the fourth row of pins, . . . , (2N+1)-th pin in the third row of pins, the (3N+1)-th pin in the fourth row of pins, the first pin in the first row of pins, the (N+1)-th pin in the second row of pins, . . . , (S4N−1) the (K−1)-th pin in the first row of pins, and (S4N) the (N+K−1)-th pin in the second row of pins, K is a positive integer and 1≦K≦N, so that a distance between two pins having adjacent output order corresponds to the COF mode. 
     
     
       21. The driving circuit of  claim 1 , wherein M=4, when the first row of pins, the second row of pins, . . . , and the M-th row of pins are staggered in a second staggering way, a distance between the first pin in the first row of pins and the (N+1)-th pin in the second row of pins along the first direction<a distance between the first pin in the first row of pins and the (2N+1)-th pin in the third row of pins along the first direction<a distance between the first pin in the first row of pins and the (3N+1)-th pin in the fourth row of pins along the first direction. 
     
     
       22. A pin output order arranging method applied to a driving circuit, the driving circuit comprising (M*N) pins, the (M*N) pins comprising a first pin, a second pin, . . . , and a (M*N)-th pin, the pin output order arranging method comprising steps of:
 (a) arranging the first pin, the second pin, . . . , and an N-th pin of the (M*N) pins along a first direction in a specific distance spaced to form a first row of pins, arranging a (N+1)-th pin, a (N+2)-th pin, . . . , and an 2N-th pin of the (M*N) pins along the first direction in the specific distance spaced to form a second row of pins, . . . , and arranging a [(M−1)*N+1]-th pin, a [(M−1)*N+2]-th pin, . . . , and a (M*N)-th pin of the (M*N) pins along the first direction in the specific distance spaced to form a M-th row of pins respectively, so that the first row of pins, the second row of pins, . . . , and the M-th row of pins are staggered along a second direction in a staggering way or an aligning way, and M and N are integers larger than 1; and 
 (b) correspondingly arranging a pin output order S1˜SMN of the (M*N) pins according to different application modes of the driving circuit. 
 
     
     
       23. The pin output order arranging method of  claim 22 , wherein M=4, when an application mode of the driving circuit is a COG mode, the pin output order S1˜S4N of the (4*N) pins arranged by the step (b) is: (S1) the first pin, (S2) the (2N+1)-th pin, (S3) the (N+1)-th pin, (S4) the (3N+1)-th pin, . . . , (S4N−3) the N-th pin, (S4N−2) the 3N-th pin, (S4N−1) the 2N-th pin, and (S4N) the 4N-th pin, so that a distance between two pins having adjacent output order corresponds to the COG mode. 
     
     
       24. The pin output order arranging method of  claim 22 , wherein M=4, when an application mode of the driving circuit is a COG mode, the pin output order S1˜S4N of the (4*N) pins arranged by the step (b) is: (S1) the 4N-th pin, (S2) the 2N-th pin, (S3) the 3N-th pin, (S4) the N-th pin, . . . , (S4N−3) the (3N+1)-th pin, (S4N−2) the (N+1)-th pin, (S4N−1) the (2N+1)-th pin, and (S4N) the first pin, so that a distance between two pins having adjacent output order corresponds to the COG mode. 
     
     
       25. The pin output order arranging method of  claim 22 , wherein M=4, when an application mode of the driving circuit is a chip-on-film (COF) mode, the pin output order S1˜S4N of the (4*N) pins arranged by the step (b) is: (S1) the (3N+K)-th pin in the fourth row of pins, (S2) the (2N+K)-th pin in the third row of pins, (S3) the (3N+K−1)-th pin in the fourth row of pins, (S4) the (2N+K−1)-th pin in the third row of pins, . . . , the (3N+1)-th pin in the fourth row of pins, the (2N+1)-th pin in the third row of pins, the first pin in the first row of pins, the (N+1)-th pin in the second row of pins, . . . , the N-th pin in the first row of pins, the 2N-th pin in the second row of pins, the 4N-th pin in the fourth row of pins, the 3N-th pin in the third row of pins, . . . , (S4N−1) the (3N+K+1)-th pin in the fourth row of pins, and (S4N) the (2N+K+1)-th pin in the third row of pins, K is a positive integer and 1≦K≦N, so that a distance between two pins having adjacent output order corresponds to the COF mode. 
     
     
       26. The pin output order arranging method of  claim 22 , wherein M=4, when an application mode of the driving circuit is a COF mode, the pin output order S1˜S4N of the (4*N) pins arranged by the step (b) is: (S1) the K-th pin in the first row of pins, (S2) the (N+K)-th pin in the second row of pins, (S3) the (K+1)-th pin in the first row of pins, (S4) the (N+K+1)-th pin in the second row of pins, . . . , the 4N-th pin in the fourth row of pins, the 3N-th pin in the third row of pins, . . . , the (3N+1)-th pin in the fourth row of pins, the (2N+1)-th pin in the third row of pins, the first pin in the first row of pins, the (N+1)-th pin in the second row of pins, . . . , (S4N−1) the (K−1)-th pin in the first row of pins, and (S4N) the (N+K−1)-th pin in the second row of pins, K is a positive integer and 1≦K≦N, so that a distance between two pins having adjacent output order corresponds to the COF mode. 
     
     
       27. The pin output order arranging method of  claim 22 , wherein M=4, when the first row of pins, the second row of pins, . . . , and the M-th row of pins are staggered in a first staggering way, a distance between the first pin in the first row of pins and the (2N+1)-th pin in the third row of pins along the first direction<a distance between the first pin in the first row of pins and the (N+1)-th pin in the second row of pins along the first direction<a distance between the first pin in the first row of pins and the (3N+1)-th pin in the fourth row of pins along the first direction. 
     
     
       28. The pin output order arranging method of  claim 22 , wherein M=4, when an application mode of the driving circuit is a COG mode, the pin output order S1˜S4N of the (4*N) pins arranged by the step (b) is: (S1) the first pin, (S2) the (N+1)-th pin, (S3) the (2N+1)-th pin, (S4) the (3N+1)-th pin, . . . , (S4N−3) the N-th pin, (S4N−2) the 2N-th pin, (S4N−1) the 3N-th pin, and (S4N) the 4N-th pin, so that a distance between two pins having adjacent output order corresponds to the COG mode. 
     
     
       29. The pin output order arranging method of  claim 22 , wherein M=4, when an application mode of the driving circuit is a COG mode, the pin output order S1˜S4N of the (4*N) pins arranged by the step (b) is: (S1) the 4N-th pin, (S2) the 3N-th pin, (S3) the 2N-th pin, (S4) the N-th pin, . . . , (S4N−3) the (3N+1)-th pin, (S4N−2) the (2N+1)-th pin, (S4N−1) the (N+1)-th pin, and (S4N) the first pin, so that a distance between two pins having adjacent output order corresponds to the COG mode. 
     
     
       30. The pin output order arranging method of  claim 22 , wherein M=4, when an application mode of the driving circuit is a COF mode, the pin output order S1˜S4N of the (4*N) pins arranged by the step (b) is: (S1) the (3N+K)-th pin in the fourth row of pins, (S2) the (2N+K)-th pin in the third row of pins, (S3) the (3N+K−1)-th pin in the fourth row of pins, (S4) the (2N+K−1)-th pin in the third row of pins, . . . , the (3N+1)-th pin in the fourth row of pins, the (2N+1)-th pin in the third row of pins, the first pin in the first row of pins, the (N+1)-th pin in the second row of pins, . . . , the N-th pin in the first row of pins, the 2N-th pin in the second row of pins, the 4N-th pin in the fourth row of pins, the 3N-th pin in the third row of pins, . . . , (S4N−1) the (3N+K+1)-th pin in the fourth row of pins, and (S4N) the (2N+K+1)-th pin in the third row of pins, K is a positive integer and 1≦K≦N, so that a distance between two pins having adjacent output order corresponds to the COF mode. 
     
     
       31. The pin output order arranging method of  claim 22 , wherein M=4, when an application mode of the driving circuit is a COF mode, the pin output order S1˜S4N of the (4*N) pins arranged by the step (b) is: (S1) the K-th pin in the first row of pins, (S2) the (N+K)-th pin in the second row of pins, (S3) the (K+1)-th pin in the first row of pins, (S4) the (N+K+1)-th pin in the second row of pins, . . . , the N-th pin in the first row of pins, the 2N-th pin in the second row of pins, the 4N-th pin in the fourth row of pins, the 3N-th pin in the third row of pins, . . . , the (3N+1)-th pin in the fourth row of pins, the (2N+1)-th pin in the third row of pins, the first pin in the first row of pins, the (N+1)-th pin in the second row of pins, . . . , (S4N−1) the (K−1)-th pin in the first row of pins, and (S4N) the (N+K−1)-th pin in the second row of pins, K is a positive integer and 1≦K≦N, so that a distance between two pins having adjacent output order corresponds to the COF mode. 
     
     
       32. The pin output order arranging method of  claim 22 , wherein M=4, when the first row of pins, the second row of pins, . . . , and the M-th row of pins are staggered in a second staggering way, a distance between the first pin in the first row of pins and the (N+1)-th pin in the second row of pins along the first direction<a distance between the first pin in the first row of pins and the (2N+1)-th pin in the third row of pins along the first direction<a distance between the first pin in the first row of pins and the (3N+1)-th pin in the fourth row of pins along the first direction. 
     
     
       33. The pin output order arranging method of  claim 22 , wherein M=4, when an application mode of the driving circuit is a COG mode, the pin output order S1˜S4N of the (4*N) pins arranged by the step (b) is: (S1) the first pin, (S2) the (3N+1)-th pin, (S3) the (N+1)-th pin, (S4) the (2N+1)-th pin, . . . , (S4N−3) the N-th pin, (S4N−2) the 4N-th pin, (S4N−1) the 2N-th pin, and (S4N) the 3N-th pin, so that a distance between two pins having adjacent output order corresponds to the COG mode. 
     
     
       34. The pin output order arranging method of  claim 22 , wherein M=4, when an application mode of the driving circuit is a COG mode, the pin output order S1˜S4N of the (4*N) pins arranged by the step (b) is: (S1) the 3N-th pin, (S2) the 2N-th pin, (S3) the 4N-th pin, (S4) the N-th pin, . . . , (S4N−3) the (2N+1)-th pin, (S4N−2) the (N+1)-th pin, (S4N−1) the (3N+1)-th pin, and (S4N) the first pin, so that a distance between two pins having adjacent output order corresponds to the COG mode. 
     
     
       35. The pin output order arranging method of  claim 22 , wherein M=4, when an application mode of the driving circuit is a COF mode, the pin output order S1˜S4N of the (4*N) pins arranged by the step (b) is: (S1) the (2N+K)-th pin in the third row of pins, (S2) the (3N+K)-th pin in the fourth row of pins, (S3) the (2N+K−1)-th pin in the third row of pins, (S4) the (3N+K−1)-th pin in the fourth row of pins, . . . , the (2N+1)-th pin in the third row of pins, the first pin in the first row of pins, the (N+1)-th pin in the second row of pins, . . . , the N-th pin in the first row of pins, the 2N-th pin in the second row of pins, the 3N-th pin in the third row of pins, the 4N-th pin in the fourth row of pins, . . . , (S4N−1) the (2N+K+1)-th pin in the third row of pins, and (S4N) the (3N+K+1)-th pin in the fourth row of pins, K is a positive integer and 1≦K≦N, so that a distance between two pins having adjacent output order corresponds to the COF mode. 
     
     
       36. The pin output order arranging method of  claim 22 , wherein M=4, when an application mode of the driving circuit is a COF mode, the pin output order S1˜S4N of the (4*N) pins arranged by the step (b) is: (S1) the K-th pin in the first row of pins, (S2) the (N+K)-th pin in the second row of pins, (S3) the (K+1)-th pin in the first row of pins, (S4) the (N+K+1)-th pin in the second row of pins, . . . , the N-th pin in the first row of pins, the 2N-th pin in the second row of pins, the 3N-th pin in the third row of pins, the 4N-th pin in the fourth row of pins, . . . , the (2N+1)-th pin in the third row of pins, the (3N+1)-th pin in the fourth row of pins, the first pin in the first row of pins, the (N+1)-th pin in the second row of pins, . . . , (S4N−1) the (K−1)-th pin in the first row of pins, and (S4N) the (N+K−1)-th pin in the second row of pins, K is a positive integer and 1≦K≦N, so that a distance between two pins having adjacent output order corresponds to the COF mode. 
     
     
       37. The pin output order arranging method of  claim 22 , wherein M=4, when the first row of pins, the second row of pins, . . . , and the M-th row of pins are staggered in a third staggering way, a distance between the first pin in the first row of pins and the (3N+1)-th pin in the fourth row of pins along the first direction<a distance between the first pin in the first row of pins and the (N+1)-th pin in the second row of pins along the first direction <a distance between the first pin in the first row of pins and the (2N+1)-th pin in the third row of pins along the first direction. 
     
     
       38. The pin output order arranging method of  claim 22 , wherein M=4, when an application mode of the driving circuit is a COG mode, the pin output order S1˜S4N of the (4*N) pins arranged by the step (b) is: (S1) the first pin, (S2) the (N+1)-th pin, (S3) the (2N+1)-th pin, (S4) the (3N+1)-th pin, . . . , (S4N−3) the N-th pin, (S4N−2) the 2N-th pin, (S4N−1) the 3N-th pin, and (S4N) the 4N-th pin, so that a distance two pins having adjacent output order corresponds to the COG mode. 
     
     
       39. The pin output order arranging method of  claim 22 , wherein M=4, when an application mode of the driving circuit is a COG mode, the pin output order S1˜S4N of the (4*N) pins arranged by the step (b) is: (S1) the 4N-th pin, (S2) the 3N-th pin, (S3) the 2N-th pin, (S4) the N-th pin, . . . , (S4N−3) the (3N+1)-th pin, (S4N−2) the (2N+1)-th pin, (S4N−1) the (N+1)-th pin, and (S4N) the first pin, so that a distance between two pins having adjacent output order corresponds to the COG mode. 
     
     
       40. The pin output order arranging method of  claim 22 , wherein M=4, when an application mode of the driving circuit is a COF mode, the pin output order S1˜S4N of the (4*N) pins arranged by the step (b) is: (S1) the (2N+K)-th pin in the third row of pins, (S2) the (3N+K)-th pin in the fourth row of pins, (S3) the (2N+K−1)-th pin in the third row of pins, (S4) the (3N+K−1)-th pin in the fourth row of pins, . . . , the (2N+1)-th pin in the third row of pins, the (3N+1)-th pin in the fourth row of pins, the first pin in the first row of pins, the (N+1)-th pin in the second row of pins, . . . , the N-th pin in the first row of pins, the 2N-th pin in the second row of pins, the 3N-th pin in the third row of pins, the 4N-th pin in the fourth row of pins, . . . , (S4N−1) the (2N+K+1)-th pin in the third row of pins, and (S4N) the (3N+K+1)-th pin in the fourth row of pins, K is a positive integer and 1≦K≦N, so that a distance between two pins having adjacent output order corresponds to the COF mode. 
     
     
       41. The pin output order arranging method of  claim 22 , wherein M=4, when an application mode of the driving circuit is a COF mode, the pin output order S1˜S4N of the (4*N) pins arranged by the step (b) is: (S1) the K-th pin in the first row of pins, (S2) the (N+K)-th pin in the second row of pins, (S3) the (K+1)-th pin in the first row of pins, (S4) the (N+K+1)-th pin in the second row of pins, . . . , the N-th pin in the first row of pins, the 2N-th pin in the second row of pins, the 3N-th pin in the third row of pins, the 4N-th pin in the fourth row of pins, . . . , the (2N+1)-th pin in the third row of pins, the (3N+1)-th pin in the fourth row of pins, the first pin in the first row of pins, the (N+1)-th pin in the second row of pins, . . . , (S4N−1) the (K−1)-th pin in the first row of pins, and (S4N) the (N+K−1)-th pin in the second row of pins, K is a positive integer and 1≦K≦N, so that a distance between two pins having adjacent output order corresponds to the COF mode. 
     
     
       42. The pin output order arranging method of  claim 22 , wherein M=4, when the first row of pins, the second row of pins, . . . , and the M-th row of pins are staggered in a second staggering way, a distance between the first pin in the first row of pins and the (N+1)-th pin in the second row of pins along the first direction<a distance between the first pin in the first row of pins and the (2N+1)-th pin in the third row of pins along the first direction<a distance between the first pin in the first row of pins and the (3N+1)-th pin in the fourth row of pins along the first direction.

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