US9646835B2ActiveUtilityA1

Wafer structure for electronic integrated circuit manufacturing

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Assignee: AEROFLEX COLORADO SPRINGS INCPriority: Aug 25, 2011Filed: Mar 3, 2016Granted: May 9, 2017
Est. expiryAug 25, 2031(~5.1 yrs left)· nominal 20-yr term from priority
H10P 14/3824H10P 10/12H10P 10/00H10P 90/123H10P 72/74H10P 52/00H10P 10/128H01L 21/02013H01L 21/18H01L 27/0921H01L 21/187H01L 21/6835H01L 21/182H01L 21/304H01L 21/185H01L 29/1087H01L 27/092H10D 62/378H10D 84/854H10D 84/85
49
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Claims

Abstract

A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.

Claims

exact text as granted — not AI-modified
We claim: 
     
       1. A method of forming a wafer structure comprising:
 forming a first region in a device wafer having at least one major surface, a thickness, and a conductivity profile of a first conductivity type substantially parallel to said at least one major surface; 
 forming a second region in a separate handle wafer having a thickness, and a second conductivity profile of the first conductivity type of said first region, such second conductivity profile being substantially different than the conductivity profile of said first region, such that said second region is in electrical contact with said first region opposite the major surface of said first region; 
 bonding together said device and handle wafers; 
 forming an interface region formed between said first region and said second region; and 
 placing impurity sites in said first region, said second region, and said interface region, such impurity sites being substantially electrically inactive over a temperature range, 
 wherein the conductivity profile of said first region transitions abruptly to the conductivity profile of said second region within the interface region, 
 wherein said first region, said second region, and said interface region comprise the same semiconductor material, and 
 wherein said impurity sites are selected from the group of isotopes consisting of silicon, carbon, fluorine, sulfur, chlorine, nitrogen, or defects selected from the group consisting of lattice vacancies, interstitial defects, Frenkel defect pairs, crystal dislocations, or a combination of said isotopes and defects. 
 
     
     
       2. The method of  claim 1  further comprising thinning one or both of said bonded device and handle wafers. 
     
     
       3. The method of  claim 2  wherein thinning comprises grinding the device wafer. 
     
     
       4. The method of  claim 2  wherein thinning comprises grinding the handle wafer. 
     
     
       5. The method of  claim 2  wherein thinning comprises grinding to a predetermined thickness. 
     
     
       6. The method of  claim 2  wherein thinning comprises polishing.

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