Non-volatile memory unit and method for manufacturing the same

Abstract

A non-volatile memory unit and method of manufacturing the same are disclosed. The non-volatile memory unit includes a substrate with a source region and a drain region. A first dielectric layer forms on the substrate. An erase gate, a floating gate and couple control gate are forms on the first dielectric layer. The coupled dielectric layer are formed among and above the erase gate, the floating gate and the selective gate, and formed on the couple gate of the coupled dielectric layer.

What is claimed is: 
     
       1. A non-volatile memory unit comprising:
 a substrate, wherein a source region and a drain region are formed on the surface, and the source region and the drain region are separated apart via a channel region; 
 a first dielectric layer, formed on the substrate and defining a first pattern opening along the depth direction on the first dielectric layer; 
 an erase gate (EG), formed on the first dielectric layer and is disposed upon a projection of the first pattern opening along the depth direction; 
 a floating gate (FG), formed on the first dielectric layer and near the erase gate; 
 a selective gate (SG), formed on the first dielectric layer and near the floating gate, wherein the selective gate and the floating gate are disposed upon the channel region's projection along the depth direction; 
 a second dielectric layer, formed on the first dielectric layer and covering the erase gate and the selective gate, wherein the floating gate is disposed between two adjacent second dielectric layers; 
 a coupled dielectric layer, formed on the erase gate, the floating gate, the selective gate and the second dielectric layer; and 
 a couple gate (CG), formed on the coupled dielectric layer; 
 wherein the first pattern opening of the first dielectric layer has a first thickness, the thickness of the first dielectric layer below the projection of the floating gate (FG) is defined as a second thickness, and the thickness of the first dielectric layer below the projection of the selective gate (SG) is defined as a third thickness, 
 wherein the first thickness is thicker than the second thickness, and the second thickness is thicker than the third thickness. 
 
     
     
       2. The non-volatile memory unit of  claim 1 , wherein the projection of the relative narrow portion of the erase gate (EG) that disposed at the damascene grooves is disposed above the first pattern opening along the depth direction, and the erase gate (EG) is narrower than the first pattern opening along the horizontal direction, wherein the damascene grooves have a relative wide base that tapering upward the top. 
     
     
       3. The non-volatile memory unit of  claim 1 , wherein the second dielectric layer is disposed between the two sides of the erase gate (EG) and the second dielectric layer is formed between the erase gate (EG) and the floating gate (FG). 
     
     
       4. The non-volatile memory unit of  claim 1 , wherein the coupled dielectric layer is formed into a continuous concave and convex shape and covers the second dielectric layer, the erase gate (EG), the selective gate (SG) and the floating gate (FG), along the depth direction the coupled dielectric layer on the floating gate is relatively near the first dielectric layer corresponding to the erase gate (EG) and the selective gate (FG). 
     
     
       5. The non-volatile memory unit of  claim 1 , wherein the first dielectric layer comprises a transistor dielectric layer and a base dielectric layer. 
     
     
       6. The non-volatile memory unit of  claim 1 , wherein the second dielectric layer comprises a covering dielectric layer, a first sidewall dielectric layer and a second sidewall dielectric layer.