Power MOS transistor and manufacturing method therefor

Abstract

The present invention discloses a power Metal Oxide Semiconductor (MOS) transistor, wherein a second U-shaped trench is formed below a first U-shaped trench, so that a field oxidation stress transition region can be extended, so as to greatly reduce current leakage caused by the field oxidation stress and improve the reliability of the device; and a charge compensation region is provided in a drift region at the bottom of the second U-shaped trench, and a super-junction structure is formed between the charge compensation region and the drift region to improve the breakdown voltage of the power device. According to the present invention, the second U-shaped trench and the charge compensation region are formed by a self-aligning process, so that the technical process is simple, reliable and easy to control, and can reduce the manufacturing cost of the power MOS transistor and improve its yield.

What is claimed is: 
     
       1. A power Metal Oxide Semiconductor (MOS) transistor, comprising:
 a drain region of a first doping type in a semiconductor substrate, a drift region of the first doping type, a channel region of a second doping type, a source region of the first doping type and a first U-shaped trench, wherein the drain region is provided at a bottom of the semiconductor substrate, the drift region is provided above the drain region, the channel region is provided on both sides of side walls of the first U-shaped trench and above die drift region, a bottom of the first U-shaped trench extends into the drift region, a gate oxide layer covering the channel region is provided on, and the source region is provided at a top of the semiconductor substrate and above the channel region; 
 a channel region contact region is provided in the channel region, the doping type of the channel region contact region is die same as that of the channel region, and a doping concentration of the channel region contact region is greater than that of the channel region; 
 a second U-shaped trench in the semiconductor substrate, wherein the second U-shaped trench is provided below the first U-shaped trench, a opening width of the second U-shaped trench is smaller than that of the first U-shaped trench, and a depth of the second U-shaped trench is 10-100 nm; 
 a field oxide layer is provided hi the second U-shaped trench, a thickness of the field oxide layer is greater than that of the gate oxide layer, a charge compensation region is provided in the drift region below the field oxide layer, and the charge compensation region has the second doping type, the second U-shaped trench extends a field oxide stress transition region between the field oxide layer and the gate oxide layer, and a thickness of a bottom portion of the field oxide layer is thicker than a thickness of side portions of the field oxide layer; and 
 a polysilicon gate covering the gate oxide layer and the field oxide layer is provided in the first U-shaped trench and the second U-shaped trench. 
 
     
     
       2. The power MOS transistor of  claim 1 , wherein the channel region contact region is provided at the top of the semiconductor substrate and is adjacent to the source region, or the channel region contact region is recessed in the semiconductor substrate. 
     
     
       3. The power MOS transistor of  claim 1 , wherein an upper surface of the polysilicon gate is lower than an opening surface of the first U-shaped trench, and an insulating layer is provided above the polysilicon gate and at the top of the first U-shaped trench. 
     
     
       4. The power MOS transistor of  claim 1 , wherein the first doping type is n-type doping, and the second doping type is p-type doping; or, the first doping type is p-type doping, and the second doping type is n-type doping.