Semiconductor electrostatic discharge protection circuit, ESD protection semiconductor device, and layout structure of ESD protection semiconductor device

Abstract

An electrostatic discharge protection semiconductor device includes a substrate, a first well formed in the substrate, a second well formed in the substrate and spaced apart from the first well, a gate formed on the substrate and positioned in between the first well and the second well, a drain region formed in the first well, a source region formed in the second well, a first doped region formed in the first well and adjacent to the drain region, and a second doped region formed in the first well and spaced apart from both the first doped region and the gate. The first well, the drain region, and the source region include a first conductivity type, the second well, the first doped region and the second doped region include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.

What is claimed is: 
     
       1. An electrostatic discharge (ESD) protection semiconductor device, comprising:
 a substrate; 
 a first well formed in the substrate, and the first well comprising a first conductivity type; 
 a second well formed in the substrate and spaced apart from the first well, the second well comprising a second conductivity type, and the second conductivity type being complementary to the first conductivity type; 
 a gate formed on the substrate and positioned in between the first well and the second well; 
 a drain region formed in the first well and a source region formed in the second well, and the drain region and the source region comprising the first conductivity type; 
 a first doped region formed in the first well and adjacent to the drain region, and the first doped region comprising the second conductivity type; and 
 a second doped region formed in the first well and in between the first doped region and the gate, the second doped region being spaced apart from both the first doped region and the gate, and the second doped region comprising the second conductivity type. 
 
     
     
       2. The ESD protection semiconductor device according to  claim 1 , wherein the gate overlaps a portion of the first well and a portion of the second well. 
     
     
       3. The ESD protection semiconductor device according to  claim 1 , wherein the first doped region and the second doped region are spaced apart from each other by a shallow trench isolation (STI) or a salicide block (SAB). 
     
     
       4. The ESD protection semiconductor device according to  claim 1 , wherein the second doped region and the gate are spaced apart from each other by a STI or a portion of the first well. 
     
     
       5. The ESD protection semiconductor device according to  claim 1 , wherein the second doped region and the gate are spaced apart from each other by a blocking structure, and the blocking structure comprising a first STI and a second STI, the first STI is formed adjacent to the second doped region, and the gate overlaps a portion of the second STI. 
     
     
       6. The ESD protection semiconductor device according to  claim 5 , further comprising a third doped region formed in between the first STI and the second STI, and the third doped region comprising the first conductivity type. 
     
     
       7. The ESD protection semiconductor device according to  claim 1 , further comprising a pick-up region formed in the second well and spaced apart from the source region, and the pick-up region comprising the second conductivity type. 
     
     
       8. The ESD protection semiconductor device according to  claim 7 , wherein a concentration of the first doped region, a concentration of the second doped region and a concentration of the pick-up region are the same. 
     
     
       9. The ESD protection semiconductor device according to  claim 7 , wherein the second doped region, the source region, the pick-up region, and the gate are grounded. 
     
     
       10. The ESD protection semiconductor device according to  claim 1 , wherein the drain region and the first doped region are electrically connected to an I/O pad or a VDD pad. 
     
     
       11. A layout structure of an ESD protection semiconductor device comprising:
 a substrate; 
 a first well formed in the substrate, and the first well comprising a first conductivity type; 
 a second well formed in the substrate and spaced apart from the first well, the second well comprising a second conductivity type, and the second conductivity type being complementary to the first conductivity type; 
 a plurality of fins formed on the substrate, the fins being extended along a first direction and arranged along a second direction, and the first direction and the second direction being perpendicular; 
 a gate formed on the substrate and extended along the second direction, the gate covering a portion of each fin, a portion of the first well and a portion of the second well; 
 a plurality of drain segments respectively formed in the fins at a first side of the gate, and the drain segments comprising the first conductivity type; 
 a plurality of source segments respectively formed in the fins at a second side of the gate opposite to the first side, and the source segments comprising the first conductivity type; 
 a plurality of first doped segments formed in the fins at the first side, and the first doped segments comprising the second conductivity type; and 
 a plurality of second doped segments formed in the fins at the first side, the second doped segments comprising the second conductivity type and being spaced apart from the first doped segments and the gate. 
 
     
     
       12. The layout structure of the ESD protection semiconductor device according to  claim 11 , wherein the first doped segments are spaced apart from the second doped segments by an insulating layer and/or an undoped segment, respectively. 
     
     
       13. The layout structure of the ESD protection semiconductor device according to  claim 11 , wherein the second doped segments are spaced apart from the gate by an insulating layer and/or an undoped segment, respectively. 
     
     
       14. The layout structure of the ESD protection semiconductor device according to  claim 11 , wherein the drain segments and the first doped segments are electrically connected to an I/O pad or a VDD pad. 
     
     
       15. The layout structure of the ESD protection semiconductor device according to  claim 11 , wherein the second doped segments are grounded. 
     
     
       16. The layout structure of the ESD protection semiconductor device according to  claim 11 , wherein the source segments are grounded.