Ferroelectric memory cell sensing

Abstract

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory device may maintain a digit line voltage at a ground reference for a duration associated with biasing a ferroelectric capacitor of a memory cell. For example, a digit line that is in electronic communication with a ferroelectric capacitor may be virtually grounded while a voltage is applied to a plate of the ferroelectric capacitor, and the ferroelectric capacitor may be isolated from the virtual ground after a threshold associated with applying the voltage to the plate is reached. A switching component (e.g., a transistor) that is in electronic communication with the digit line and virtual ground may be activated to virtually ground the digit line and deactivated to isolate the digit line from virtual ground.

What is claimed is: 
     
       1. A method of operating a ferroelectric memory cell, comprising:
 virtually grounding a digit line that is in electronic communication with a ferroelectric capacitor of the ferroelectric memory cell and a virtual ground; 
 applying a voltage to a plate of the ferroelectric capacitor while the digit line is virtually grounded and before sensing a logic state of the ferroelectric memory cell as part of a read operation; 
 determining that a threshold associated with a rate of change of the voltage of the plate has been reached; and 
 isolating the digit line from the virtual ground after applying the voltage to the plate of the ferroelectric capacitor and after the threshold associated with applying the voltage is reached. 
 
     
     
       2. The method of  claim 1 ,
 wherein the threshold is associated with a magnitude of the voltage of the plate. 
 
     
     
       3. The method of  claim 1 , wherein virtually grounding the digit line comprises:
 activating a switching component that is in electronic communication with the digit line and the virtual ground, and wherein isolating the digit line from the virtual ground comprises:
 deactivating the switching component. 
 
 
     
     
       4. The method of  claim 3 , wherein deactivating the switching component comprises:
 reducing a linear equalization voltage applied to the switching component that is in electronic communication with the digit line and the virtual ground. 
 
     
     
       5. The method of  claim 4 , further comprising:
 activating a selection component that is in electronic communication with the ferroelectric capacitor for a sense operation of the ferroelectric memory cell after the linear equalization voltage is reduced. 
 
     
     
       6. The method of  claim 5 , wherein activating the selection component comprises:
 applying a voltage to a word line in electronic communication with the ferroelectric memory cell. 
 
     
     
       7. A method, comprising:
 virtually grounding a digit line that is in electronic communication with a ferroelectric capacitor of a ferroelectric memory cell and a virtual ground, wherein virtually grounding the digit line comprises activating a switching component that is in electronic communication with the digit line and the virtual ground; 
 applying a voltage to a plate of the ferroelectric capacitor while the digit line is virtually grounded; 
 isolating the digit line from the virtual ground after applying the voltage to the plate of the ferroelectric capacitor and after a threshold associated with applying the voltage is reached, wherein isolating the digit line from the virtual ground comprises deactivating the switching component, wherein deactivating the switching component comprises reducing a linear equalization voltage applied to the switching component that is in electronic communication with the digit line and the virtual ground; and 
 activating a selection component that is in electronic communication with the ferroelectric capacitor for a sense operation of the ferroelectric memory cell after the linear equalization voltage is reduced, wherein activating the selection component comprises applying a voltage to a word line in electronic communication with the ferroelectric memory cell, wherein the voltage applied to the word line is increased while the linear equalization voltage is reduced. 
 
     
     
       8. A method, comprising:
 virtually grounding a digit line that is in electronic communication with a ferroelectric capacitor of a ferroelectric memory cell and a virtual ground, wherein virtually grounding the digit line comprises activating a switching component that is in electronic communication with the digit line and the virtual ground; 
 applying a voltage to a plate of the ferroelectric capacitor while the digit line is virtually grounded; and 
 isolating the digit line from the virtual ground after applying the voltage to the plate of the ferroelectric capacitor and after a threshold associated with applying the voltage is reached, wherein isolating the digit line from the virtual ground comprises deactivating the switching component, wherein deactivating the switching component comprises reducing a linear equalization voltage applied to the switching component that is in electronic communication with the digit line and the virtual ground, wherein the voltage applied to the plate is increased while the linear equalization voltage is reduced. 
 
     
     
       9. The method of  claim 4 , wherein the threshold is associated with a duration following the application of the voltage to the plate of the ferroelectric capacitor. 
     
     
       10. The method of  claim 9 , wherein the duration is determined based at least in part on a timing associated with reading or writing to the ferroelectric memory cell or a timing associated with removing a parasitic voltage from the digit line, or both. 
     
     
       11. The method of  claim 9 , wherein the duration is less than or equal to three nanoseconds. 
     
     
       12. The method of  claim 1 , wherein applying the voltage to the plate of the ferroelectric capacitor comprises:
 ramping the voltage applied to the plate of the ferroelectric capacitor. 
 
     
     
       13. The method of  claim 1 , wherein the voltage applied to the plate of the ferroelectric capacitor is ramped from zero volts to a fraction of a source voltage for an array, and wherein the ferroelectric memory cell comprises a portion of the array. 
     
     
       14. A method of operating a ferroelectric memory cell, comprising:
 activating a switching component that is in electronic communication with a digit line and a virtual ground; 
 applying a voltage to a ferroelectric capacitor of the ferroelectric memory cell before sensing a logic state of the ferroelectric memory cell as part of a read operation, the ferroelectric memory cell in electronic communication with the digit line; 
 determining that a rate of change of a voltage of a plate satisfies a threshold; 
 deactivating the switching component after applying the voltage to the ferroelectric capacitor based at least in part on determining that the threshold is satisfied; and 
 selecting the ferroelectric memory cell after deactivating the switching component. 
 
     
     
       15. The method of  claim 14 , wherein activating the switching component comprises:
 applying a voltage to the switching component, and wherein deactivating the switching component comprises:
 removing the voltage from the switching component. 
 
 
     
     
       16. The method of  claim 14 , wherein the switching component is deactivated based at least in part on determining a magnitude of the voltage of the plate of the ferroelectric capacitor has reached a second threshold. 
     
     
       17. The method of  claim 14 , wherein selecting the ferroelectric memory cell comprises:
 applying a voltage to a selection component that is in electronic communication with the ferroelectric capacitor and the digit line. 
 
     
     
       18. The method of  claim 14 , further comprising:
 determining a duration between applying the voltage to the ferroelectric capacitor and deactivating the switching component. 
 
     
     
       19. The method of  claim 18 , wherein the duration is determined based at least in part on:
 a characteristic of the ferroelectric memory cell, 
 a characteristic of the digit line, 
 a timing associated with reading or writing to the ferroelectric memory cell, 
 a full dump window size determined based at least in part on a measured difference between a voltage of the digit line resulting from a first state stored by the ferroelectric capacitor and a voltage of the digit line resulting from a second stored state stored by the ferroelectric capacitor, 
 or any combination thereof. 
 
     
     
       20. An electronic memory apparatus, comprising:
 a ferroelectric memory cell that comprises a ferroelectric capacitor in electronic communication with a digit line; and 
 a controller in electronic communication with the ferroelectric memory cell and operable to: 
 virtually ground the digit line that is in electronic communication with the ferroelectric capacitor of the ferroelectric memory cell and a virtual ground; 
 apply a voltage to a plate of the ferroelectric capacitor while the digit line is virtually grounded and before sensing a logic state of the ferroelectric memory cell as part of a read operation; 
 determine that a threshold associated with a rate of change of the voltage of the plate has been reached; and 
 isolate the digit line from the virtual ground after applying the voltage to the plate of the ferroelectric capacitor and after the threshold associated with applying the voltage is reached. 
 
     
     
       21. The electronic memory apparatus of  claim 20 , further comprising:
 a switching component that is in electronic communication with the digit line and the virtual ground, wherein the controller is operable to: 
 activate the switching component; and
 deactivate the switching component. 
 
 
     
     
       22. The electronic memory apparatus of  claim 21 , further comprising:
 a linear equalization component that is in electronic communication with the switching component. 
 
     
     
       23. The electronic memory apparatus of  claim 22 , wherein the controller is operable to:
 activate a selection component that is in electronic communication with the ferroelectric capacitor for a sense operation of the ferroelectric memory cell, wherein a timing of the sense operation is based at least in part on a linear equalization voltage. 
 
     
     
       24. The electronic memory apparatus of  claim 20 , wherein the controller is operable to:
 determine a duration between applying the voltage to the plate of the ferroelectric capacitor and isolating the digit line. 
 
     
     
       25. The electronic memory apparatus of  claim 20 , wherein the controller is operable to:
 apply a voltage to a word line in electronic communication with the ferroelectric memory cell.