Method of making a plurality of semiconductor devices

Abstract

A method of making a plurality of semiconductor devices comprising a chip scale packages. The method includes providing a semiconductor wafer having a major surface and a backside. The method also includes forming a plurality of contacts on the major surface. The method further includes forming a plurality of trenches in the major surface of the substrate. The method also includes forming a plurality of openings in the wafer between the backside and the trenches in the major surface. The method further includes depositing an encapsulant on the backside of the wafer. At least some of the encapsulant passes through the openings in the wafer to at least partially fill the trenches in the major surface. The method also includes singulating the wafer to produce a plurality of chip scale packages having a major surface including one or more contacts and side walls at least partially covered with said encapsulant.

The invention claimed is: 
     
       1. A method of making a plurality of semiconductor devices comprising chip scale packages, the method comprising:
 providing a semiconductor wafer having a major surface and a backside; 
 forming a plurality of contacts on the major surface; 
 forming a plurality of trenches in the major surface of the substrate; 
 forming a plurality of openings in the wafer between the backside and the trenches in the major surface; 
 depositing an encapsulant on the backside of the wafer, wherein at least some of the encapsulant passes through the openings in the wafer to at least partially fill the trenches in the major surface; and 
 singulating the wafer along the trenches to produce said plurality of chip scale packages, each chip scale package having the major surface including one or more of the contacts and side walls at least partially covered with the encapsulant. 
 
     
     
       2. The method of  claim 1 , wherein said forming of the openings in the wafer between the backside and the trenches in the major surface comprises forming a plurality of trenches in the backside of the wafer, and wherein the openings are formed at intersections between the trenches in the major surface and the trenches in the backside of the wafer. 
     
     
       3. The method of  claim 2 , wherein the trenches in the backside of the substrate and in the major surface of the substrate are arranged in a grid. 
     
     
       4. The method  claim 3 , wherein the trenches in the backside have a pitch that is the same as a pitch of the trenches in the major surface. 
     
     
       5. The method  claim 3 , wherein the trenches in the backside are offset with respect to the trenches in the major surface when viewed from above the major surface. 
     
     
       6. The method of  claim 5 , wherein the offset between the trenches in the back side and the trenches in the major surface is substantially equal to one half the pitches of the trenches in the back side and the trenches in the major surface. 
     
     
       7. The method of  claim 2 , wherein the wafer has a thickness T wafer , wherein the trenches in the major surface have a depth d major  and the trenches in the backside have a depth d backside , and wherein d major +d backside >T wafer . 
     
     
       8. The method of  claim 1 , wherein said forming the plurality of openings in the wafer between the backside of the wafer and the trenches in the major surface comprises forming a plurality of holes extending between the backside of the wafer and the trenches in the major surface. 
     
     
       9. The method of  claim 1 , further comprising removing material from the backside of the wafer until the trenches in the major surface of the substrate are exposed. 
     
     
       10. The method of  claim 1 , further comprising placing a protective foil over the contacts on the major surface prior to depositing the encapsulant.