US9893013B2ExpiredUtilityA1

Semiconductor device and a method of increasing a resistance value of an electric fuse

57
Assignee: RENESAS ELECTRONICS CORPPriority: Mar 7, 2006Filed: Oct 20, 2016Granted: Feb 13, 2018
Est. expiryMar 7, 2026(expired)· nominal 20-yr term from priority
H10W 42/80H10W 20/497H10W 20/49H10W 20/4421H10W 20/435H10W 20/425H10W 20/48H10W 20/43H10W 20/493H01H 85/041H01L 2924/0002H01L 23/5329H01L 23/5283H01L 23/53238H01L 23/528H01L 23/525H01L 23/5227H01L 23/62H01L 23/53228H01L 23/5256H01L 2924/00
57
PatentIndex Score
0
Cited by
61
References
10
Claims

Abstract

A semiconductor device having an electric fuse structure which receives an electric current to permit the electric fuse to be cut without damaging portions around the fuse. The electric fuse can be electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.

Claims

exact text as granted — not AI-modified
We claim: 
     
       1. A semiconductor device, comprising: a semiconductor substrate;
 an interlayer dielectric formed on the semiconductor substrate: 
 a plurality of metal wiring layers formed over the interlayer dielectric and including a fine layer having the smallest wiring width and thickness among the metal wiring layers: 
 a first insulating layer formed in the fine layer: 
 a first trench formed in the first insulating layer; 
 an electric fuse formed in the first trench and structured to be cut by applying an electrical current to the electric fuse; 
 a second insulating layer formed over the electric fuse and the first insulating layer; 
 a second trench formed in the second insulating layer: 
 a wiring formed in the second trench; and 
 a third insulating layer formed between the electric fuse and the second Insulating layer such that the third insulating layer directly contacts the electric fuse, the third insulating layer having a smaller thickness than the first insulating layer; and 
 wherein a thickness of the electric fuse is smaller than a thickness of the wiring, and wherein the electric fuse includes: 
 a copper film; and 
 a barrier film having a higher melting point than the copper film, formed between the copper film and side and bottom surfaces of the first trench. 
 
     
     
       2. The semiconductor device according to the  claim 1 ,
 wherein the barrier film includes Ta. 
 
     
     
       3. The semiconductor device according to the  claim 2 ,
 wherein the barrier film includes first and second harrier films at the side surface of the first trench, 
 wherein the first barrier film includes Ta, and 
 wherein the second barrier film includes TaN. 
 
     
     
       4. The semiconductor device according to the  claim 3 ,
 wherein the third insulating film includes first and second films, 
 wherein the first film includes Si and O, and 
 wherein the second film includes Si, C and N. 
 
     
     
       5. The semiconductor device according to the  claim 1 ,
 wherein the third insulating film includes first and second films, 
 wherein the first film includes Si and O, and 
 wherein the second film includes Si, C and N. 
 
     
     
       6. The semiconductor device according to the  claim 1 , further comprising a gate electrode layer covered with the interlayer dielectric. 
     
     
       7. The semiconductor device according to the  claim 1 , wherein the first insulating layer has a relative dielectric constant of 3 or less. 
     
     
       8. The semiconductor device according to the  claim 1 , wherein the metal wiring layers further including a semiglobal layer formed over the fine layer and having wirings with larger wiring widths and a larger thicknesses than wirings of metal wiring layers in the fine layer. 
     
     
       9. The semiconductor device according to the  claim 8 , wherein the metal wiring layers further including a global layer formed over the semiglobal layer and having wirings with larger wiring widths and larger thicknesses than wirings of metal wiring layers in the semiglobal layer. 
     
     
       10. The semiconductor device according to the  claim 1 , wherein a linear expansion coefficient of the electric fuse is higher than that of the first insulating layer and the third insulating layer.

Cited by (0)

No later patents cite this yet.

References (0)

No backward citations on record.