Semiconductor substrate and fabrication method thereof

Abstract

A method for fabricating a semiconductor substrate is disclosed, which includes: forming a first dielectric layer on a substrate body; forming a plurality of first vias penetrating the first dielectric layer to expose portions of the substrate body; forming a second dielectric layer on the first dielectric layer and the exposed portions of the substrate body, wherein the second dielectric layer extends on walls of the first vias; etching the second dielectric layer to form a plurality of openings communicating with the first vias and form a plurality of second vias penetrating the second dielectric layer in the first vias so as to expose portions of the substrate body, leaving the second dielectric layer on the walls of the first vias; and forming a circuit layer in the openings, and forming a plurality of conductive vias in the second vias for electrically connecting the circuit layer and the substrate body.

What is claimed is: 
     
       1. A semiconductor substrate, comprising:
 a substrate body; 
 a first dielectric layer formed on the substrate body and having a plurality of first vias exposing portions of the substrate body; 
 a second dielectric layer formed on the first dielectric layer and in the first vias, wherein a plurality of openings are each formed in the second dielectric layer and extend into the first dielectric layer to communicate with the first vias, each of the openings having a bottom surface and a side wall surface adjacent to the bottom surface, the first dielectric layer and the second dielectric layer form the side wall surface of each of the openings, a thickness of the first dielectric layer is smaller than a sum of a depth of the opening and the first via, an interface between the first dielectric layer and the second dielectric layer is lower than a top end of the opening, and a plurality of second vias are formed to penetrate the second dielectric layer in the first vias so as to expose portions of the substrate body, leaving the second dielectric layer on walls of the first vias; 
 a circuit layer formed in the openings and in direct contact with the first dielectric layer and the second dielectric layer forming the side wall surface of each of the openings; and 
 a plurality of conductive vias formed in the second vias for electrically connecting the circuit layer and the substrate body. 
 
     
     
       2. The substrate of  claim 1 , wherein the first dielectric layer and the second dielectric layer are made of silicon oxide. 
     
     
       3. The substrate of  claim 1 , wherein the circuit layer and the conductive vias are made of copper.