Raised e-fuse

Abstract

A semiconductor device with a semiconductor-on-insulator (SOI) structure is provided including an insulating layer and a semiconductor layer formed on the insulating layer and a fuse. The fuse includes a first at least partially silicided raised semiconductor region with a first silicided portion and, adjacent to the first at least partially silicided raised semiconductor region, a second at least partially silicided raised semiconductor region with a second silicided portion. The second silicided portion is formed in direct physical contact with the first silicided portion.

What is claimed: 
     
       1. A semiconductor device, comprising
 a semiconductor-on-insulator (SOI) structure comprising an insulating layer and a semiconductor layer formed on said insulating layer; and 
 a fuse, said fuse comprising:
 a first at least partially silicided raised semiconductor region with a first silicided portion; and 
 adjacent to said first at least partially silicided raised semiconductor region, a second at least partially silicided raised semiconductor region with a second silicided portion, wherein said second silicided portion is formed in direct physical contact with said first silicided portion. 
 
 
     
     
       2. The semiconductor device of  claim 1 , wherein said second raised semiconductor region is formed partially overlapping said first raised semiconductor region. 
     
     
       3. The semiconductor device of  claim 1 , wherein said second raised semiconductor region is formed in physical contact with said first raised semiconductor region. 
     
     
       4. The semiconductor device of  claim 1 , wherein said first silicided portion is formed overlapping said second silicided portion. 
     
     
       5. The semiconductor device of  claim 1 , wherein said first silicided portion is formed overlapping said second raised semiconductor region. 
     
     
       6. The semiconductor device of  claim 1 , wherein said semiconductor layer comprises silicon and said first and second raised semiconductor regions comprise epitaxial semiconductor material. 
     
     
       7. The semiconductor device of  claim 6 , wherein said epitaxial semiconductor material comprises silicon-germanium. 
     
     
       8. The semiconductor device of  claim 6 , wherein said epitaxial semiconductor material comprises silicon. 
     
     
       9. The semiconductor device of  claim 1 , further comprising a field effect transistor separated from said fuse by an isolation region, wherein said field effect transistor comprises a channel region made of a portion of said semiconductor layer and a raised source/drain region made of the same material as said first or second at least partially silicided raised semiconductor region. 
     
     
       10. The semiconductor device of  claim 1 , further comprising:
 an additional insulating layer positioned over said silicided semiconductor layer and silicided raised semiconductor regions; and 
 contacts embedded in said additional insulating layer and contacting said silicided raised semiconductor regions. 
 
     
     
       11. A semiconductor device, comprising
 a semiconductor-on-insulator (SOI) structure comprising an insulating layer and a semiconductor layer formed on said insulating layer; and 
 a fuse, said fuse comprising:
 a first at least partially silicided raised semiconductor region with a first silicided portion; and 
 adjacent to said first at least partially silicided raised semiconductor region, a second at least partially silicided raised semiconductor region with a second silicided portion, wherein said second raised semiconductor region partially overlaps said first raised semiconductor region. 
 
 
     
     
       12. The semiconductor device of  claim 11 , wherein said first silicided portion is formed overlapping said second silicided portion. 
     
     
       13. The semiconductor device of  claim 11 , wherein said first silicided portion is formed overlapping said second raised semiconductor region. 
     
     
       14. The semiconductor device of  claim 11 , wherein said semiconductor layer comprises silicon and said first and second raised semiconductor regions comprise epitaxial semiconductor material. 
     
     
       15. The semiconductor device of  claim 14 , wherein said epitaxial semiconductor material comprises silicon-germanium. 
     
     
       16. The semiconductor device of  claim 14 , wherein said epitaxial semiconductor material comprises silicon. 
     
     
       17. The semiconductor device of  claim 11 , further comprising a field effect transistor separated from said fuse by an isolation region, wherein said field effect transistor comprises a channel region made of a portion of said semiconductor layer and a raised source/drain region made of the same material as said first or second at least partially silicided raised semiconductor region. 
     
     
       18. The semiconductor device of  claim 11 , further comprising:
 an additional insulating layer positioned over said silicided semiconductor layer and silicided raised semiconductor regions; and 
 contacts embedded in said additional insulating layer and contacting said silicided raised semiconductor regions.