Array substrate, liquid crystal display panel, and its liquid crystal display device

Abstract

The present invention provides an array substrate. The array substrate includes a base substrate, a first metal layer, an insulating layer, and a second metal layer subsequently formed on the base substrate. The first metal layer is scan lines or charge sharing lines of the array substrate. The second metal layer is one of a source electrode and drain electrode of a charge sharing thin film transistor of the array substrate. The first metal layer, the second metal layer, and the insulating layer between them stack together to forma charge sharing capacitor of the array substrate. The present invention further provides the liquid crystal display panel and the liquid crystal display device with the above-mentioned array substrate. By means of array substrate, the present invention can increase the pixel aperture ratio.

The invention claimed is: 
     
       1. An array substrate, comprising a base substrate, a first metal layer, an insulating layer, and a second metal layer subsequently formed on the base substrate,
 wherein the first metal layer is scan lines or charge sharing lines of the array substrate, 
 wherein the second metal layer is one of a source electrode and drain electrode of a charge sharing thin film transistor of the array substrate, 
 wherein the first metal layer, the second metal layer, and the insulating layer between them are stacked together to form a charge sharing capacitor of the array substrate; and 
 wherein the array substrate is divided to a plurality of pixel units, each of the pixel units includes a main pixel region, a sub pixel region, and a trace region between the two pixel regions, each of the pixel units is connected to one of the scanning lines and one of the charge sharing lines, one of the scanning lines and one of the charge sharing lines are disposed side by side in the trace region, and the first metal forming the charge sharing capacitor is the charge sharing line of the array substrate. 
 
     
     
       2. The array substrate as claimed in  claim 1 , wherein the array substrate includes a plurality of the scanning lines along a row direction, and a plurality of the charge sharing lines,
 wherein the pixel unit of the nth row is electrically connected to the scanning line of the nth row, and the second metal layer of the pixel unit of the nth row is insulated from and overlapped with the charge sharing line of the nth row, wherein n is a positive integer. 
 
     
     
       3. The array substrate as claimed in  claim 1 , wherein the pixel unit of the array substrate is a Tri-gate structure, and the first metal forming the charge sharing capacitor is the scanning line. 
     
     
       4. The array substrate as claimed in  claim 3 , wherein the array substrate includes a plurality of the scanning lines along row direction, the pixel unit of the mth row is electrically connected to the scanning line of the mth row, and the second metal layer of the pixel unit of the mth row is insulated from and overlapped with the scanning line of the (m+1)th row, wherein m is a positive integer. 
     
     
       5. The array substrate as claimed in  claim 1 ,
 wherein the array substrate further includes a plurality of data lines along a column direction, a first thin film transistor, a first storage capacitor, a second thin film transistor, and a second storage capacitor, 
 wherein in the first thin film transistor, a gate electrode is electrically connected to the scanning lines, a source electrode is electrically connected to the data lines, and a drain electrode is electrically connected to one end of the first storage capacitor, 
 wherein the other end of the first storage capacitor is electrically connected to a common electrode, 
 wherein in the second thin film transistor, a gate electrode is electrically connected to the scanning lines, a source electrode is electrically connected to the data lines, and a drain electrode is electrically connected to one end of the second storage capacitor, 
 wherein the other end of the second storage capacitor is electrically connected to the common electrode, and 
 wherein in the charge sharing thin film transistor, a gate electrode is electrically connected to the charge sharing line, the other one of a source electrode and a drain electrode is electrically connected to the drain electrode of the second thin film transistor. 
 
     
     
       6. The array substrate as claimed in  claim 5 , wherein the second metal layer forming the charge sharing capacitor is connected to the common electrode through a via hole. 
     
     
       7. A liquid crystal display panel, wherein the liquid crystal display panel includes an array substrate, a color filter substrate opposite to the array substrate, and liquid crystal disposed between the array substrate and the color filter substrate,
 wherein the array substrate includes a base substrate, a first metal layer, an insulating layer, and a second metal layer subsequently formed on the substrate, 
 wherein the first metal layer is scan lines or charge sharing lines of the array substrate, 
 wherein the second metal layer is one of a source electrode and drain electrode of a charge sharing thin film transistor of the array substrate, 
 wherein the first metal layer, the second metal layer, and the insulating layer between them are stacked together to form a charge sharing capacitor of the array substrate; and 
 wherein the array substrate is divided to a plurality of pixel units, each of the pixel units includes a main pixel region, a sub pixel region, and a trace region between the two pixel regions, each of the pixel units is connected to one of the scanning lines and one of the charge sharing lines, one of the scanning lines and one of the charge sharing lines are disposed side by side in the trace region, and the first metal forming the charge sharing capacitor is the charge sharing line of the array substrate. 
 
     
     
       8. The liquid crystal display panel as claimed in  claim 7 ,
 wherein the array substrate includes a plurality of the scanning lines along a row direction, and a plurality of the charge sharing lines, 
 wherein the pixel unit of the nth row is electrically connected to the scanning line of the nth row, and the second metal layer of the pixel unit of the nth row is insulated from and overlapped with the charge sharing line of the nth row, wherein n is a positive integer. 
 
     
     
       9. The liquid crystal display panel as claimed in  claim 7 , wherein the pixel unit of the array substrate is a Tri-gate structure, and the first metal forming the charge sharing capacitor is the scanning line. 
     
     
       10. The liquid crystal display panel as claimed in  claim 9 , wherein the array substrate includes a plurality of the scanning lines along row direction, the pixel unit of the mth row is electrically connected to the scanning line of the mth row, and the second metal layer of the pixel unit of the mth row is insulated from and overlapped with the scanning line of the (m+1)th row, wherein m is a positive integer. 
     
     
       11. The liquid crystal display panel as claimed in  claim 7 ,
 wherein the array substrate further includes a plurality of data lines along a column direction, a first thin film transistor, a first storage capacitor, a second thin film transistor, and a second storage capacitor, 
 wherein in the first thin film transistor, a gate electrode is electrically connected to the scanning lines, a source electrode is electrically connected to the data lines, and a drain electrode is electrically connected to one end of the first storage capacitor, 
 wherein the other end of the first storage capacitor is electrically connected to a common electrode, 
 wherein in the second thin film transistor, a gate electrode is electrically connected to the scanning lines, a source electrode is electrically connected to the data lines, and a drain electrode is electrically connected to one end of the second storage capacitor, 
 wherein the other end of the second storage capacitor is electrically connected to the common electrode, and 
 wherein in the charge sharing thin film transistor, a gate electrode is electrically connected to the charge sharing line, the other one of a source electrode and a drain electrode is electrically connected to the drain electrode of the second thin film transistor. 
 
     
     
       12. The liquid crystal display panel as claimed in  claim 11 , wherein the second metal layer forming the charge sharing capacitor is connected to the common electrode through a via hole. 
     
     
       13. A liquid crystal display device, wherein the liquid crystal display device includes a liquid crystal display panel and a light source module providing light to the liquid crystal display panel,
 wherein the liquid crystal display panel includes an array substrate, a color filter substrate opposite to the array substrate, and liquid crystal disposed between the array substrate and the color filter substrate, 
 wherein the array substrate includes a base substrate, a first metal layer, an insulating layer, and a second metal layer subsequently formed on the substrate, 
 wherein the first metal layer is scan lines or charge sharing lines of the array substrate, 
 wherein the second metal layer is one of a source electrode and drain electrode of a charge sharing thin film transistor of the array substrate, 
 wherein the first metal layer, the second metal layer, and the insulating layer between them are stacked together to form a charge sharing capacitor of the array substrate; and 
 wherein the array substrate is divided to a plurality of pixel units, each of the pixel units includes a main pixel region, a sub pixel region, and a trace region between the two pixel regions, each of the pixel units is connected to one of the scanning lines and one of the charge sharing lines, one of the scanning lines and one of the charge sharing lines are disposed side by side in the trace region, and the first metal forming the charge sharing capacitor is the charge sharing line of the array substrate. 
 
     
     
       14. The liquid crystal display device as claimed in  claim 13 ,
 wherein the array substrate includes a plurality of the scanning lines along a row direction, and a plurality of the charge sharing lines, 
 wherein the pixel unit of the nth row is electrically connected to the scanning line of the nth row, and the second metal layer of the pixel unit of the nth row is insulated from and overlapped with the charge sharing line of the nth row, wherein n is a positive integer. 
 
     
     
       15. The liquid crystal display device as claimed in  claim 13 , wherein the pixel unit of the array substrate is a Tri-gate structure, and the first metal forming the charge sharing capacitor is the scanning line. 
     
     
       16. The liquid crystal display device as claimed in  claim 15 , wherein the array substrate includes a plurality of the scanning lines along row direction, the pixel unit of the mth row is electrically connected to the scanning line of the mth row, and the second metal layer of the pixel unit of the mth row is insulated from and overlapped with the scanning line of the (m+1)th row, wherein m is a positive integer. 
     
     
       17. The liquid crystal display device as claimed in  claim 13 ,
 wherein the array substrate further includes a plurality of data lines along a column direction, a first thin film transistor, a first storage capacitor, a second thin film transistor, and a second storage capacitor, 
 wherein in the first thin film transistor, a gate electrode is electrically connected to the scanning lines, a source electrode is electrically connected to the data lines, and a drain electrode is electrically connected to one end of the first storage capacitor, 
 wherein the other end of the first storage capacitor is electrically connected to a common electrode, 
 wherein in the second thin film transistor, a gate electrode is electrically connected to the scanning lines, a source electrode is electrically connected to the data lines, and a drain electrode is electrically connected to one end of the second storage capacitor, 
 wherein the other end of the second storage capacitor is electrically connected to the common electrode, and 
 wherein in the charge sharing thin film transistor, a gate electrode is electrically connected to the charge sharing line, the other one of a source electrode and a drain electrode is electrically connected to the drain electrode of the second thin film transistor, 
 
       wherein the second metal layer forming the charge sharing capacitor is connected to the common electrode through a via hole.