Semiconductor device and method of manufacturing semiconductor device

Abstract

A semiconductor includes a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, and a gate electrode. The gate electrode has a first portion arranged with the second semiconductor region in a direction perpendicular to a first direction extending from the first electrode to the first semiconductor region, and has a second portion on the first portion. The semiconductor also includes a gate insulating layer between the gate electrode and each of the three semiconductor regions. The gate insulating layer extends to the upper surface of the third semiconductor region to form an extending portion. The second portion of the gate electrode protrudes in an upward direction from the upper surface of the extending portion of the gate insulating layer, and a lower part of the second portion of the gate electrode is embedded in the first portion of the gate electrode.

What is claimed is: 
     
       1. A semiconductor device comprising:
 a first electrode; 
 a first semiconductor region of a first conductivity type provided on the first electrode; 
 a second semiconductor region of a second conductivity type provided on the first semiconductor region; 
 a third semiconductor region of the first conductivity type selectively provided on the second semiconductor region; 
 a gate electrode including:
 a first portion including polycrystalline silicon and arranged with the second semiconductor region in a second direction perpendicular to a first direction extending from the first electrode to the first semiconductor region and 
 a second portion including metal and provided on a part of the first portion; 
 
 a gate insulating layer provided between the gate electrode and each of the first semiconductor region, the second semiconductor region, and the third semiconductor region, the gate insulating layer extends to the upper surface of the third semiconductor region to form an extending portion; 
 a first insulating portion provided on another part of the first portion and being adjacent to the second portion in the second direction; 
 a second insulating portion provided on the second portion and on the first insulating portion; and 
 a second electrode provided on the third semiconductor region and on the second insulating portion, and arranged with the second portion in the second direction, wherein 
 the second portion of the gate electrode protrudes upwardly from the upper surface of the extending portion of the gate insulating layer, and a lower part of the second portion of the gate electrode is embedded in the polycrystalline silicon of the first portion of the gate electrode. 
 
     
     
       2. The semiconductor device according to  claim 1 , wherein the second portion is surrounded by the another part of the first portion outside a groove. 
     
     
       3. The semiconductor device according to  claim 1 , wherein a length of the second portion in the first direction is shorter than a length of the first portion in the first direction. 
     
     
       4. The semiconductor device according to  claim 1 , wherein one end of the second portion in the first direction is aligned with the third semiconductor region along a line in the second direction from the one end of the second portion. 
     
     
       5. The semiconductor device according to  claim 1 , wherein a part of the first insulating portion and a part of the second insulating portion are provided on the third semiconductor region. 
     
     
       6. The semiconductor device according to  claim 1 , wherein the second semiconductor region, the third semiconductor region, and the gate electrode extend in a third direction perpendicular to the first direction and the second direction. 
     
     
       7. The semiconductor device according to  claim 1 , wherein the second portion is in contact with the first portion. 
     
     
       8. The semiconductor device according to  claim 1 , wherein one end of the second portion in the first direction is aligned with any of the first semiconductor region and the second semiconductor region along a line in the second direction from the one end of the second portion. 
     
     
       9. The semiconductor device according to  claim 1 , further comprising:
 a fourth semiconductor region of the second conductivity type selectively provided on the second semiconductor region, 
 wherein a carrier concentration of the second conductivity type in the fourth semiconductor region is higher than a carrier concentration of the second conductivity type in the second semiconductor region. 
 
     
     
       10. The semiconductor device according to  claim 1 , wherein a lower part of the second portion in the first direction is aligned with the fourth semiconductor region along a line in the second direction from the one end of the second portion. 
     
     
       11. The semiconductor device according to  claim 1 , further comprising:
 a fifth semiconductor region of the first conductivity type provided below the first semiconductor region, 
 wherein a carrier concentration of the first conductivity type in the fifth semiconductor region is higher than a carrier concentration of the first conductivity type in the first semiconductor region. 
 
     
     
       12. A method of manufacturing a semiconductor device comprising:
 forming a first semiconductor region of a first conductivity type on a first electrode; 
 forming a second semiconductor region of a second conductivity type on the first semiconductor region; 
 forming a third semiconductor region of the first conductivity type on the second semiconductor region; 
 forming a gate electrode, the gate electrode including:
 a first portion including polycrystalline silicon and arranged with the second semiconductor region in a second direction perpendicular to a first direction extending from the first electrode to the first semiconductor region and 
 a second portion including metal and provided on a part of the first portion; 
 
 forming a gate insulating layer between the gate electrode and each of the first semiconductor region, the second semiconductor region, and the third semiconductor region, before forming the gate electrode; 
 forming a first insulating portion on another part of the first portion and the first insulating portion surrounding the second portion; 
 forming a second insulating portion on the second portion and on the first insulating portion; and 
 forming a second electrode on the third semiconductor region and on the second insulating portion, and the second electrode is arranged with the second portion in the second direction, wherein 
 the gate insulating layer extends to the upper surface of the third semiconductor region to form an extending portion, and 
 the second portion of the gate electrode protrudes upwardly from the upper surface of the extending portion of the gate insulating layer, and a lower part of the second portion of the gate electrode is embedded in the polycrystalline silicon of the first portion of the gate electrode. 
 
     
     
       13. The method of manufacturing a semiconductor device according to  claim 12 , wherein the second portion is surrounded by the another part of the first portion outside a groove.