Semiconductor devices having fin active regions

Abstract

Semiconductor devices are providing including a first isolation region configured to define a first fin active region protruding from a substrate, first gate patterns on the first fin active region, and a first epitaxial region in the first fin active region between the first gate patterns. Sidewalls of the first epitaxial region have first inflection points so that an upper width of the first epitaxial region is greater than a lower width of the first epitaxial region.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 a first isolation region defining a first fin active region protruding from a substrate; 
 first gate patterns on the first fin active region; and 
 a first epitaxial region in the first fin active region between the first gate patterns, 
 wherein sidewalls of the first epitaxial region comprise first inflection points so that an upper width of the first epitaxial region is greater than a lower width of the first epitaxial region; 
 wherein lower portions of the sidewalls of the first epitaxial region below the first inflection points are vertically flat; and 
 wherein the first fin active region comprises a plurality of fin active regions connected in a bridge shape. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein a width of the first epitaxial region adjacent to a surface of the first fin active region is a maximum width therein. 
     
     
       3. The semiconductor device of  claim 1 , further comprising an air space between the first fin active region and the first isolation region. 
     
     
       4. The semiconductor device of  claim 1 , further comprising:
 a second fin active region protruding from the substrate; 
 second gate patterns on the second fin active region; and 
 a second epitaxial region in the second fin active region between the second gate patterns, 
 wherein the second epitaxial region is wider and deeper than the first epitaxial region. 
 
     
     
       5. The semiconductor device of  claim 4 , wherein sidewalls of the second epitaxial region comprise second inflection points so that an upper width of the second epitaxial region is greater than a lower width of the second epitaxial region. 
     
     
       6. The semiconductor device of  claim 4 :
 wherein the first epitaxial region comprises at least one of silicon (Si) and silicon carbide (SiC); and 
 the second epitaxial region comprises silicon-germanium (SiGe). 
 
     
     
       7. The semiconductor device of  claim 1 , wherein each of the first gate patterns comprises:
 first interface insulating layers on a surface of the first fin active region; 
 first gate electrodes on the first interface insulating layers; 
 first gate barrier layers surrounding outer sidewalls and bottom surfaces of the first gate electrodes in a U-shape; 
 first gate insulating layers surrounding outer sidewalls and bottom surfaces of the first gate barrier layers in a U-shape; and 
 first spacers on outer sidewalls of the first gate insulating layers. 
 
     
     
       8. A semiconductor device, comprising:
 an isolation region defining a first fin active region and a second fin active region that protrudes from a substrate; 
 first gate patterns on the first fin active region and second gate patterns on the second fin active region; and 
 a first source/drain region in the first fin active region between the first gate patterns and a second source/drain region in the second fin active region between the second gate patterns, 
 wherein the second source/drain region comprises sidewalls having inflection points so that an upper width of the second source/drain region is greater than a lower width of the second source/drain region; and 
 wherein the device further comprises: 
 first gate spacers on sidewalls of the first gate patterns; and 
 second gate spacers on sidewalls of the second gate patterns, 
 wherein the first gate spacers are thinner than the second gate spacers. 
 
     
     
       9. The semiconductor device of  claim 8 , wherein the first source/drain region comprises sidewalls that are vertically flat and substantially vertically aligned with interfaces between the first gate patterns and the first gate spacers. 
     
     
       10. The semiconductor device of  claim 8 , wherein the sidewalls of the second source/drain region vertically overlap and align with the second gate spacers. 
     
     
       11. The semiconductor device of  claim 8 , wherein the first source/drain region has sidewalls having inflection points so that an upper width of the first source/drain region is greater than a lower width thereof. 
     
     
       12. A semiconductor device, comprising:
 gate patterns extending in parallel with each other in a first direction; and 
 source/drain regions between the gate patterns, the source/drain regions having upper and lower portions and the lower portion having sidewalls that are vertically flat, 
 wherein the upper and lower portions of the source/drain regions are separated by inflection points so that a width of the upper portion is greater than a width of the lower portion; and 
 wherein the device further comprises fin active regions extending in parallel with each other in a second direction, perpendicular to the first direction so as to intersect the gate patterns, wherein the gate patterns comprise butting gate patterns overlapping both ends of the fin active regions. 
 
     
     
       13. The semiconductor device of  claim 12 , further comprising:
 gate spacers on sidewalls of the gate patterns, wherein the sidewalls of the lower portion of the source/drain regions are substantially vertically aligned with interfaces between the gate patterns and the gate spacers. 
 
     
     
       14. The semiconductor device of  claim 13 , further comprising an isolation region defining the fin active regions protruding from a substrate. 
     
     
       15. The semiconductor device of  claim 14 , wherein the fin active region comprises a plurality of fin active regions connected in a bridge shape. 
     
     
       16. The semiconductor device of  claim 15 , further comprising an air space between the fin active region and the isolation region.