Semiconductor device for manufacturing

Abstract

A semiconductor device includes an active pattern protruding from a substrate, gate structures crossing over the active pattern, gate spacers on sidewalls of the gate structures, a source/drain region in the active pattern between the gate structures, and a source/drain contact on and connected to the source/drain region. The source/drain contact includes a first portion between the gate structures and being in contact with the gate spacers, a second portion on the first portion and not being in contact with the gate spacers, and a third portion on the second portion. A first boundary between the second and third portions is at the substantially same height as a top surface of the gate structure.

What is claimed is: 
     
       1. A semiconductor device comprising:
 an active pattern; 
 a gate structure crossing over the active pattern; 
 a gate spacer on a sidewall of the gate structure; 
 a source/drain region on the active pattern at a side of the gate structure; 
 a source/drain contact on the source/drain region and connected to the source/drain region; and 
 a gas-permeable layer between the gate spacer and the source/drain contact, 
 wherein the source/drain contact comprises: 
 a first portion at a side of the gate structure, the first portion being in contact with the gate spacer; 
 a second portion on the first portion, the second portion being spaced apart from the gate spacer; and 
 a third portion on the second portion, 
 wherein a first boundary between the second and third portions is at substantially a same height as a top surface of the gate structure; and 
 wherein the gas-permeable layer extends to contact the source/drain region. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein the first portion is connected to the second portion and the second portion is connected to the third portion such that the first, second, and third portions constitute one body. 
     
     
       3. The semiconductor device of  claim 1 , further comprising:
 an insulating layer between the second portion and the gas-permeable layer. 
 
     
     
       4. The semiconductor device of  claim 1 , wherein the active pattern extends in a first direction,
 wherein the gate structure extends in a second direction intersecting the first direction, 
 wherein a first width of the first portion is greater than a second width of the second portion when viewed from a cross-sectional view taken along the first direction. 
 
     
     
       5. The semiconductor device of  claim 4 , wherein a third width of the first portion is greater than a fourth width of the second portion when viewed from a cross-sectional view taken along the second direction. 
     
     
       6. The semiconductor device of  claim 4 , wherein a third width of the first portion is smaller than a fourth width of the second portion when viewed from a cross-sectional view taken along the second direction. 
     
     
       7. The semiconductor device of  claim 6 , wherein the second portion includes an extension at a lower level than a second boundary between the first and second portions, and
 wherein the extension is spaced apart from the first portion. 
 
     
     
       8. The semiconductor device of  claim 4 , wherein a profile of a first sidewall of the first portion and a second sidewall of the second portion adjacent thereto is discontinuous when viewed from a cross-sectional view taken along the second direction, and
 wherein a profile of the second sidewall and a third sidewall of the third portion adjacent thereto is continuous when viewed from the cross-sectional view taken along the second direction. 
 
     
     
       9. The semiconductor device of  claim 1 , wherein the source/drain region comprises:
 a lower portion being in contact with the active pattern, the lower portion having substantially negatively inclined sidewalls; and 
 an upper portion extending from the lower portion, the upper portion having substantially positively inclined sidewalls. 
 
     
     
       10. The semiconductor device of  claim 9 , wherein air gaps are formed under the sidewalls of the lower portion. 
     
     
       11. The semiconductor device of  claim 1 , wherein the active pattern includes a plurality of active patterns,
 wherein the source/drain region includes a plurality of source/drain regions respectively on the plurality of active patterns, and 
 wherein the source/drain contact crosses over the plurality of active patterns and is connected in common to the plurality of source/drain regions. 
 
     
     
       12. The semiconductor device of  claim 1 , further comprising a device isolation pattern defining the active pattern and wherein the gas-permeable layer extends to contact the device isolation pattern. 
     
     
       13. The semiconductor device of  claim 12 , wherein a lower sidewall of the source/drain region is spaced apart from the gas-permeable layer to provide an air gap between the lower sidewall of the source/drain region and the gas-permeable layer. 
     
     
       14. The semiconductor device of  claim 1 , wherein the gas-permeable layer is configured to enable gases produced by hydrocarbon ashing to pass therethrough. 
     
     
       15. A semiconductor device comprising:
 active patterns protruding from a substrate, the active patterns extending in a first direction, and the active patterns arranged along a second direction intersecting the first direction; 
 gate structures extending in the second direction and crossing over the active patterns; 
 gate spacers on sidewalls of the gate structures; 
 a plurality of source/drain regions respectively on the active patterns between the gate structures; 
 a source/drain contact connected to at least one source/drain region of the plurality of source/drain regions; and 
 a gas-permeable layer between the source/drain contact and one of the gate spacers, 
 wherein the source/drain contact comprises: 
 a first portion being in contact with the at least one source/drain region; 
 a second portion extending from the first portion, the second portion at a lower level than top surfaces of the gate structures; and 
 a third portion extending from the second portion, the third portion at a higher level than the top surfaces of the gate structures, 
 wherein a first width of the first portion is greater than a second width of the second portion when viewed from a cross-sectional view taken along the first direction; and 
 wherein the gas-permeable layer is in contact with the source/drain region. 
 
     
     
       16. A semiconductor device comprising:
 an active fin on a substrate; 
 a gate structure crossing over the active fin; 
 a source/drain region on the substrate adjacent the gate structure; 
 a source/drain contact on the source/drain region and connected to the source/drain region, wherein the source/drain contact comprises a first portion in contact with the source/drain region and a second portion on the first portion; and 
 a gas-permeable capping layer on an upper surface of the first portion of the source/drain contact, wherein the second portion of the source/drain contact extends through the gas-permeable capping layer to contact the first portion of the source/drain contact, 
 wherein the gas-permeable capping layer extends to contact a sidewall of the first portion and the source/drain region. 
 
     
     
       17. The semiconductor device of  claim 16 , wherein the gate structure comprises a gate spacer, and the gas-permeable capping layer extends along a vertical sidewall of the gate spacer. 
     
     
       18. The semiconductor device of  claim 16 , wherein the second portion of the source/drain contact has a width that increases as a distance from the substrate increases. 
     
     
       19. The semiconductor device of  claim 16 , wherein the second portion of the source/drain contact has a width at an interface with the first portion of the source/drain contact that is less than a width of the first portion of the source/drain contact. 
     
     
       20. The semiconductor device of  claim 16 , wherein the gas-permeable capping layer comprises a silicon oxide layer or a porous silicon oxy-hydrocarbon layer.