Semiconductor device and method of fabricating the same

Abstract

A semiconductor device and a method of fabricating the same are provided. The semiconductor device comprises a first multi-channel active pattern which is defined by a field insulating layer, extends along a first direction, and includes a first portion and a second portion; a gate electrode which extends along a second direction different from the first direction and is formed on the first portion; and a first source/drain region which is formed around the second portion protruding further upward than a top surface of the field insulating layer and contacts the field insulating layer, wherein the second portion is disposed on both sides of the first portion in the first direction and is more recessed than the first portion, a top surface of the first portion and a top surface of the second portion protrude further upward than the top surface of the field insulating layer, and a profile of sidewalls of the second portion is continuous.

We claim: 
     
       1. A semiconductor device comprising:
 a substrate which comprises a first region and a second region; 
 a first transistor which is formed in the first region; and 
 a second transistor which is formed in the second region, 
 wherein the first transistor comprises a first multi-channel active pattern which is defined by a field insulating layer, extends along a first direction, and includes a first portion and a second portion; a first gate electrode which extends along a second direction different from the first direction and is formed on the first portion; and a first source/drain region which is formed on both sides of the first gate electrode to contact a top surface and sidewalls of the second portion protruding further upward than a top surface of the field insulating layer and contacts the field insulating layer, 
 wherein the second transistor comprises a second multi-channel active pattern which is defined by the field insulating layer, extends along a third direction, and includes a third portion and a fourth portion; a second gate electrode which extends along a fourth direction different from the third direction and is formed on the third portion; and a second source/drain region which is formed on both sides of the second gate electrode to contact a top surface and sidewalls of the fourth portion protruding further upward than the top surface of the field insulating layer, contacts the field insulating layer, and has a different conductivity type from that of the first source/drain region, and 
 wherein the second portion is more recessed than the first portion, a top surface of the first portion and the top surface of the second portion protrude further upward than the top surface of the field insulating layer, the fourth portion is more recessed than the third portion, a top surface of the third portion and the top surface of the fourth portion protrude further upward than the top surface of the field insulating layer, a profile of the sidewalls of the second portion is continuous, and a profile of the sidewalls of the fourth portion is continuous. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein a region in which the first source/drain region and the field insulating layer contact each other is the first region, and a region in which the second source/drain region and the field insulating layer contact each other is the second region, and
 wherein an area of the second region and an area of the first region are different from each other. 
 
     
     
       3. A semiconductor device comprising:
 a substrate which comprises a first region and a second region; 
 a first transistor which is formed in the first region; and 
 a second transistor which is formed in the second region, 
 wherein the first transistor comprises a first multi-channel active pattern which is defined by a field insulating layer, extends along a first direction, and includes a first portion and a second portion; a first gate electrode which extends along a second direction different from the first direction and is formed on the first portion; first fin spacers which are formed on part of sidewalls of the second portion protruding further than a top surface of the field insulating layer; and a first source/drain region which is formed on both sides of the first gate electrode to contact a top surface and the sidewalls of the second portion protruding further than the first fin spacers, 
 wherein the second transistor comprises a second multi-channel active pattern which is defined by the field insulating layer, extends along a third direction, and comprises a third portion and a fourth portion; a second gate electrode which extends along a fourth direction different from the third direction and is formed on the third portion; second fin spacers which are formed on part of sidewalls of the fourth portion protruding further upward than the top surface of the field insulating layer; and a second source/drain region which is formed on both sides of the second gate electrode to contact a top surface and the sidewalls of the fourth portion protruding further upward than the top surface of the field insulating layer and has a different conductivity type from that of the first source/drain region, and 
 wherein the second portion is more recessed than the first portion, a top surface of the first portion and the top surface of the second portion protrude further upward than the top surface of the field insulating layer, the fourth portion is more recessed than the third portion, and a top surface of the third portion and the top surface of the fourth portion protrude further upward than the top surface of the field insulating layer. 
 
     
     
       4. The semiconductor device of  claim 3 , wherein a bottommost part of the first source/drain region is formed along topmost parts of the first fin spacers. 
     
     
       5. The semiconductor device of  claim 3 , wherein the second source/drain region partially covers the second fin spacers. 
     
     
       6. The semiconductor device of  claim 3 , wherein the second source/drain region contacts the field insulating layer. 
     
     
       7. A semiconductor device comprising:
 a substrate which comprises a first region and a second region; 
 a first transistor which is formed in the first region; and 
 a second transistor which is formed in the second region, 
 wherein the first transistor comprises a first multi-channel active pattern which is defined by a field insulating layer, extends along a first direction, and includes a first portion and a second portion; a first gate electrode which extends along a second direction different from the first direction and is formed on the first portion; and a first source/drain region which is formed on both sides of the first gate electrode to contact a top surface and sidewalls of the second portion protruding further upward than a top surface of the field insulating layer and contacts the field insulating layer, 
 wherein the second transistor comprises a second multi-channel active pattern which is defined by the field insulating layer, extends along a third direction, and includes a third portion and a fourth portion; a second gate electrode which extends along a fourth direction different from the third direction and is formed on the third portion; and a second source/drain region which is formed on the fourth portion on both sides of the second gate electrode, and 
 wherein the second portion is more recessed than the first portion, a top surface of the first portion and the top surface of the second portion protrude further upward than the top surface of the field insulating layer, a top surface of the third portion protrudes further upward than the top surface of the field insulating layer, the top surface of the fourth portion does not protrude further upward than the top surface of the field insulating layer, and a profile of the sidewalls of the second portion is continuous. 
 
     
     
       8. The semiconductor device of  claim 7 , wherein the top surface of the field insulating layer and the top surface of the fourth portion lie in the same plane. 
     
     
       9. The semiconductor device of  claim 7 , wherein the top surface of the fourth portion is more recessed than the top surface of the field insulating layer.