Trench capacitor for high density dynamic RAM

Abstract

A dynamic one-transistor read/write memory cell employs a trench capacitor to increase the magnitude of the stored charge. The trench is etched into the silicon surface at a diffused N+ capacitor region similar to the N+ bit line, then thick oxide is grown over the bit line and over the capacitor region, but not in the trench; a partial etch followed by regrowth of oxide is used prior to the final etch for most of the depth of the trench, to thereby reduce the effect of undercut. The upper plate of the capacitor is a polysilicon layer extending into the trench and also forming field plate isolation over the face of the silicon bar. A refractory metal word line forms the gate of the access transistor at a hole in the polysilicon field plate.

What is claimed: 
     
       1. A dynamic memory cell formed in a face of a semiconductor body, said cell comprising: an access transistor having a source-to-drain path at a channel area of said face, and a metal gate over said channel area separated therefrom by a thin gate oxide;   a bit line including an elongated N+ region of said face, the drain of said transistor being an edge of said N+ region;   a metal word line extending along said face perpendicular to said bit line, said metal gate being a part of said word line;   said N+ region of said bit line being insulated from said word line by thick thermal field oxide overlying said bit line;   a capacitor area at said face including a trench etched into said face and N+ region surrounding said trench, with a thick thermal field oxide overlying said N+ region;   a region of thermal field oxide encircling said trench inset into said N+ region surrounding said trench,   a field plate including a conductive layer covering said face overlying said capacitor area, said bit line and all areas except said channel area of said transistor, and extending down into said trench to provide the upper plate of the capacitor, insulated from the silicon in said trench by a thin oxide.   
     
     
       2. A memory cell according to claim 1 wherein said field plate is insulated from said face in areas except said capacitor area and said bit line by a layer of oxide and a layer of silicon nitride. 
     
     
       3. A memory cell according to claim 1 wherein said capacitor area is spaced laterally along said face from said drain region by said channel area, and said N+ region in said capacitor area forms the source of said transistor. 
     
     
       4. A memory cell according to claim 1 wherein said field oxide over said bit line is about the same thickness as the field oxide in said capacitor area. 
     
     
       5. A memory cell according to claim 1 wherein a coating of insulator over said field plate fills said trench to provide a level surface for said metal word line. 
     
     
       6. A memory cell according to claim 1 wherein the width of said trench is no more than about one micron and the depth of the trench is at least about twice the width. 
     
     
       7. A memory cell according to claim 1 wherein said body is P type silicon, said metal word line is molybdenum, and said conductive layer is polysilicon. .Iadd. 
     
     
       8.  A dynamic memory cell formed in a face of a semiconductor body, said cell comprising: an access transistor having a source-to-drain path at a channel area of said face, and a gate over said channel area separated therefrom by a thin gate oxide;   a bit line including an elongated N+ region of said face, the drain of said transistor being an edge of said N+ region;   a word line extending along said face perpendicular to said bit line, said gate being a part of said word line;   said N+ region of said bit line being insulated from said word line by thick thermal field oxide overlying said bit line;   a capacitor area at said face including a trench etched into said face and N+ region surrounding said trench, with a thick thermal field oxide overlying said N+ region;   a region of thermal field oxide encircling said trench inset into said N+ region surrounding said trench, a field plate including a conductive layer covering said face overlying said capacitor area, said bit line and all areas except said channel area of said transistor, and extending down into said trench to provide the capacitor, insulated from the silicon in said trench by a thin oxide. .Iaddend. .Iadd.9. A memory cell according to claim 8 wherein said field plate is insulated from said face in areas except said capacitor area and said bit line by a layer of oxide and a layer of silicon nitride. .Iaddend. .Iadd.10. A memory cell according to claim 8 wherein said capacitor area is spaced laterally along said face from said drain region by said channel area, and said N+ region in said capacitor area forms the source of said transistor. .Iaddend. .Iadd.11. A memory cell according to claim 8 wherein said field oxide over said bit line is about the same thickness as the field oxide in said capacitor area. .Iaddend. .Iadd.12. A memory cell according to claim 8 wherein a coating of insulator over said field plate fills said trench to provide a level surface for said metal word line. .Iaddend. .Iadd.13. A memory cell according to claim 8 wherein the width of said trench is no more than about one micron and the depth of the trench is at least about twice the width. .Iaddend. .Iadd.14. A memory cell according to claim 8 wherein said body is P type silicon, said word line is molybdenum, and said conductive layer is polysilicon. .Iaddend.