Method of making a chip carrier with terminating resistive elements

Abstract

A generic chip carrier is described which includes, as integral parts, a voltage bus and a plurality of terminating resistors connected between the voltage bus and signal traces on the carrier. The voltage bus wraps around the chip carrier, thus providing a large area of metal. Through the selective use of the terminating resistors, the generic carrier can be customized for a particular type of integrated circuit, i.e., source or destination termination of signals. A signal trace may be customized by "opening" the terminating resistor with a current spike applied by a standard electrical probe. Spare bonding pads and terminating resistors are placed at intervals about the periphery of the carrier as insurance against defective or mistakenly removed terminating resistors.

What is claimed is: 
     
       1. A method of fabricating an integrated circuit chip carrier, comprising the steps of: a) providing a first substrate having a location defined for receiving the integrated circuit;   b) .[.metallizing a portion.]. .Iadd.depositing a metal layer on at least two surfaces .Iaddend.of said first substrate such that a voltage bus .Iadd.with a large surface area .Iaddend.is created;   c) defining at least one conductive signal path on said first substrate; and   d) depositing at least one resistive element on said first substrate such that said resistive element is connected between said conductive signal path and said voltage bus. .[.2. The method of claim 1, wherein the metallizing step (b) further comprises depositing a metal layer onto a plurality of surfaces of said first substrate, such that said voltage bus   
     
     
        occupies a large surface area..]. 3. The method of claim 1, further comprising the step of opening said resistive element with an excessive 
     
     
        electrical current. 4. The method of claim 1, further comprising the step 
     
     
        of opening said resistive element with a laser. 5. .[.The method of claim 1, further comprising the step of.]. .Iadd.A method of fabricating an integrated circuit chip carrier, comprising the steps of: (a) providing a first substrate having a location defined for receiving the integrated circuit;   (b) metallizing a portion of said first substrate such that a voltage bus is created;   (c) defining at least one conductive signal path on said first substrate;   (d) depositing at least one resistive element on said first substrate such that said resistive element is connected between said conductive signal path and said voltage bus; and   (e) adding at least one uncommitted resistive element connected to said voltage bus on said first substrate, thereby providing a spare resistive   
     
     
        element. 6. The method of claim 5, further comprising the step of connecting said uncommitted resistive element to said conductive signal 
     
     
        path when said resistive element is unavailable. 7. The method of claim 1 wherein the steps are performed in any order.