Semiconductor memory device with active pull up

Abstract

A MOS dynamic type RAM comprises memory cells (10), dummy cells (11), bit line pairs (BL, BL), word lines (WL), dummy word lines (DWL) and sense amplifiers (12). In a non-active cycle, the potentials of each pair of bit lines (BL, BL) are precharged at 1/2 of a supply potential V CC . Each sense amplifier (12) operates in an active cycle following the non-active cycle, while each active pull-up circuit (13) pulls up the potential of a higher level one of the pair of bit lines to V CC . This active cycle is defined by an internal RAS internal signal, which is generated by a NAND circuit (27) in response to an external RAS signal and an RPW signal obtained by delaying the external RAS signal by a delay circuit (20) and having a trailing edge obtained by delaying the trailing edge of the external RAS signal by a prescribed period.

What is claimed is: 
     
       1. A semiconductor memory device comprising: a plurality of pairs of bit lines;   a plurality of word lines provided to intersect with said plurality of pairs of bit lines;   a plurality of memory cells each provided in correspondence to the intersection point between each said pair of bit lines and each said word line to be connected with said pair of bit lines and said word line;   precharge means provided for each said pair of bit lines to precharge potentials of said pair of bit .[.lies173  .Iadd.lines .Iaddend.at a first constant potential;   memory cell selection/readout means for selecting a memory cell for reading data by selecting said word line after precharging of said pair of bit lines by said precharge means and reading data from said selected memory cell on said pair of bit lines;   sense amplifier means provided for each said pair of bit lines for detecting potentials of said pair of bit lines upon reading of said data from said selected memory cell to lower the potential of a lower level one of said pair of bit lines to a second constant potential;   means for supplying an external row address strobe signal having a constant duration;   delay means for delaying said external row address strobe signal by a prescribed period;   internal row address strobe signal generating means for generating an internal row address strobe signal having a trailing edge obtained by delaying the trailing edge of said external row address strobe signal by said prescribed period in response to said external row address strobe signal and the output from said delay means, said internal row address strobe signal alternately repeatedly .Iadd.defining a non-active cycle for the operation of said .Iaddend.precharge means and an active cycle for the operations of said memory cell selection/readout means and said sense amplifier means; and   active pull-up means provided for each said pair of bit lines for pulling up said potential of said higher level one of said pair of bit lines from starting of the operation of said sense amplifier means to termination of said active cycle defined by said internal row address strobe signal to a third contact potential.   
     
     
       2. A semiconductor memory device in accordance with claim 1, wherein said first and third constant potentials are at a supply potential level and said second constant potential is at a ground potential level.   
     
     
       3. A semiconductor memory device in accordance with claim 1, wherein said second constant potential is at a ground potential level and said third constant potential is at a supply potential level, while said first constant potential is at an intermediate potential level between said second constant potential and said third constant potential.   
     
     
       4. A semiconductor memory device in accordance with claim 1, wherein said delay means is formed by a plurality of inverters connected in the series form.   
     
     
       5. A semiconductor memory device in accordance with claim 1, wherein said internal row address strobe signal generating means is a NAND circuit for receiving said external row address strobe signal and the output from said delay means. .Iadd.   
     
     
       6.  A semiconductor memory device comprising: a plurality of pairs of bit lines;   a plurality of word lines provided to intersect with said plurality of pairs of bit lines;   a plurality of memory cells each provided in correspondence to the intersection point between each said pair of bit lines and each said word line to be connected with said pair of bit lines and said word line;   precharge means provided for each said pair of bit lines to precharge potentials of said pair of bit lines at a first constant potential;   a memory cell selection/readout means for selecting a memory cell for reading data by selecting said word line after precharging of said pair of bit lines by said precharge means and reading data from said selected memory cell on said pair of bit lines;   sense amplifier means provided for each said pair of bit lines for detecting potentials of said pair of bit lines upon reading of said data from said selected memory cell to lower the potential of a lower level one of said pair of bit lines to a second constant potential;   means for supplying an external row address strobe signal having a constant duration;   delay means for delaying said external row address strobe signal by a prescribed period;   internal control signal generating means for generating an internal control signal having a trailing edge obtained by delaying the trailing edge of said external row address strobe signal by said prescribed period in response to said external row address strobe signal and the output from said delay means, said internal control signal alternately repeatedly controlling a non-active cycle for the operation of said precharge means and an active cycle for the operations of said memory cell selection/readout means and said sense amplifier means; and   active pull-up means provided for each said pair of bit lines for pulling up said potential of said higher level one of said pair of bit lines after starting of the operation of said sense amplifier means to termination of said active cycle defined by said internal control signal to a third constant potential. .Iaddend. .Iadd.   
     
     
       7.  A semiconductor memory device in accordance with claim 6, wherein said second constant potential is at a ground potential level and said third constant potential is at a supply potential level, while said first constant potential is at an intermediate potential level between said second constant potential and said third constant potential. .Iaddend. .Iadd.8. A semiconductor memory device in accordance with claim 6, wherein   said delay means comprises a plurality of inverters connected in series. .Iaddend. .Iadd.9. A semiconductor memory device in accordance with claim 6, wherein   said internal control signal generating means comprises a NAND circuit for receiving said external row address strobe signal and the output from said delay means. .Iaddend. .Iadd.10. A semiconductor memory device in accordance with claim 6, wherein said internal control signal controls at least said precharge means, said sense amplifier means and said active   
     
     
        pull-up means. .Iaddend. .Iadd.11.  A semiconductor memory device comprising: a plurality of memory cells arranged in a matrix having rows and columns;   a plurality of word lines arranged in rows, wherein each word line is connected to respective ones of said memory cells arranged in a corresponding row of said matrix;   a plurality of pairs of bit lines arranged in columns, wherein one bit line of each pair of bit lines is connected to respective ones of said memory cells arranged in a corresponding column of said matrix;   a plurality of sense amplifier means arranged in columns, wherein each sense amplifier means is connected to a pair of said bit lines arranged in a corresponding column, for detecting a difference between potentials appearing on said pair of bit lines arranged in the corresponding column and pulling down a potential of a lower level bit line of said pair of bit lines to a lower constant potential;   a plurality of active pull-up means arranged in columns, wherein each active pull-up means is connected to said pair of bit lines arranged in the corresponding column, for pulling up the potential of the higher level bit line of said pair of bit lines, which is detected by said sense amplifier means as the difference between potentials to a higher constant potential;   means for receiving an external row address strobe signal having a first edge changing from a first level to a second level and a second edge changing from said second level to said first level; and   means for generating an active pull-up activating signal having a first edge changing from a third level to a fourth level and a second edge changing from said fourth level to said third level, wherein said active pull-up activating signal is connected for activating said active pull-up means in a time between the first edge thereof and the second edge thereof, the first edge of said active pull-up activating signal occurring after detecting by said sense amplifier of a difference between potentials appearing on said pair of bit lines, the second edge of said active pull-up activating signal occurring at a time after passing of a predetermined period from occurrence of said second edge of said external   
     
     
        row address strobe signal. .Iaddend. .Iadd.12.  A semiconductor memory device in accordance with claim 11, wherein said lower constant potential is at a ground potential level and said higher constant potential is at a 
     
     
        supply potential level. .Iaddend. .Iadd.13.  A semiconductor memory device in accordance with claim 11, including means of obtaining the second edge of said active pull-up activating signal by delaying the second edge of said external row address strobe signal by said predetermined period in response to the second edge of said external row address strobe signal. .Iaddend. .Iadd.14. A semiconductor memory device in accordance with claim 11, further comprising means for generating a sense amplifier activating signal having a first edge changing from a fifth level to a sixth level and a second edge changing from said sixth level to said fifth level, wherein said sense amplifier activating signal is connected for activating said sense amplifier means in a time between the first edge thereof and the second edge thereof, the first edge of said sense amplifier activating signal occurring at a time between occurrence of the first edge of said external row strobe signal and occurrence of the first edge of said active pull-up activating signal, the second edge of said means sense amplifier activating signal occurring at substantially the same time as the occurrence of said second edge of said active pull-up activating signal. .Iaddend.