Integrated circuit SRAM cell layouts

Abstract

Integrated circuit SRAM cells include a semiconductor substrate having a field region and first, second, third and fourth active regions therein. The first and second active regions each include a horizontal leg and a vertical leg and are mirror images of each other about a vertical axis. The third and fourth active regions each also include a horizontal leg and a vertical leg and are mirror images of each other about a vertical axis. The integrated circuit SRAM cells also include first and second vertically extending gate conductive layers on the semiconductor substrate. The first vertically extending conductive layer extends vertically over the first active region horizontal leg and extends vertically over the third active region horizontal leg. The second vertically extending conductive layer extends vertically over the second active region horizontal leg and extends vertically over the fourth active region horizontal leg. Accordingly, the gate conductive layers are formed perpendicular to the horizontal legs of the active regions, so that the process alignment margin is large in the longitudinal direction of the active regions. A high integration density may thereby be produced.

That which is claimed: 
     
       1. An integrated circuit .[.nonvolatile memory.]. .Iadd.SRAM .Iaddend.cell comprising: a semiconductor substrate having a field region and first, second, third and fourth active regions therein, said first and second active regions each including a horizontal leg and a vertical leg which define a vertex therebetween, such that said horizontal leg extends horizontally from the vertex and said vertical leg extends vertically from the vertex, said first and second active regions being mirror images of each other about a vertical axis, said third and fourth active regions each including a horizontal leg and a vertical leg which define a vertex therebetween, such that said horizontal leg extends horizontally from the vertex and said vertical leg extends vertically from the vertex, said third and fourth active regions being mirror images of each other about a vertical axis; and   first and second vertically extending gate conductive layers on said semiconductor substrate, said first vertically extending conductive layer extending vertically over said first active region horizontal leg and extending vertically over said third active region horizontal leg, and said second vertically extending conductive layer extending vertically over said second active region horizontal leg and extending vertically over said fourth active region horizontal leg.   
     
     
       2. An integrated circuit .[.nonvolatile memory.]. .Iadd.SRAM .Iaddend.cell according to claim 1 wherein the second active region horizontal leg includes an end, opposite the second active region vertical leg, and wherein said first vertically extending gate conductive layer further extends horizontally to the end of the second active region horizontal leg. 
     
     
       3. An integrated circuit .[.nonvolatile memory.]. .Iadd.SRAM .Iaddend.cell according to claim 2 wherein said second vertically extending gate conductive layer further extends horizontally to the vertex of the third active region horizontal and vertical legs. 
     
     
       4. An integrated circuit .[.nonvolatile memory.]. .Iadd.SRAM .Iaddend.cell according to claim 1 further comprising a horizontally extending word line, and wherein said word line and said first and second vertically extending gate conductive layers are all formed from a single conductive layer. 
     
     
       5. An integrated circuit .[.nonvolatile memory.]. .Iadd.SRAM .Iaddend.cell according to claim 4 wherein said single conductive layer is a single polysilicon layer. 
     
     
       6. An integrated circuit SRAM cell according to claim 1 wherein the first active region horizontal leg includes an end, opposite the first active region vertical leg and wherein the second active region horizontal leg includes an end, opposite the second active region vertical leg, said integrated circuit SRAM cell further comprising first and second vertically extending interconnection lines, the first vertically extending interconnection line connecting the end of the first active region horizontal leg to the vertex of the third active region horizontal and vertical legs, the second vertically extending interconnection line connecting the end of the second active region horizontal leg to the vertex of the fourth active region horizontal and vertical legs. 
     
     
       7. An integrated circuit .[.nonvolatile memory.]. .Iadd.SRAM .Iaddend.cell according to claim 6 wherein the third active region horizontal leg includes an end, opposite the third active region vertical leg and wherein the fourth active region horizontal leg includes an end, opposite the fourth active region vertical leg, said integrated circuit .[.nonvolatile memory.]. .Iadd.SRAM .Iaddend.cell further comprising a U-shaped Vss line which connects the end of the third active region horizontal leg to the end of the fourth active region horizontal leg, said U-shaped Vss line including two vertically extending legs, a respective one of which extends from a respective end of said third active region horizontal leg and said fourth active region horizontal leg, and a horizontally extending base region which connects said two vertically extending legs. 
     
     
       8. An integrated circuit .[.nonvolatile memory.]. .Iadd.SRAM .Iaddend.cell according to claim 7 wherein said first and second vertically extending interconnection lines and said U-shaped Vss line are all formed from a single conductive layer. 
     
     
       9. An integrated circuit .[.nonvolatile memory.]. .Iadd.SRAM .Iaddend.cell according to claim 8 wherein said single conductive layer Is a single polysilicon layer. 
     
     
       10. An integrated circuit .[.nonvolatile memory.]. .Iadd.SRAM .Iaddend.cell according to claim 1 wherein the first active region vertical leg includes an end, opposite the first active region horizontal leg and wherein the second active region vertical leg includes an end, opposite the second active region horizontal leg, said integrated circuit .[.nonvolatile memory.]. .Iadd.SRAM .Iaddend.cell further comprising first and second vertically extending bit lines and first and second vertically extending Vcc lines, said first vertically extending Vcc line being connected to the end of the first active region vertical leg, said second vertically extending Vcc line being connected to the end of the second active region vertical leg, said first vertically extending bit line being connected to the vertical leg of the third active region, and said second vertically extending bit line being connected to the vertical leg of the fourth active region. 
     
     
       11. An integrated circuit .[.nonvolatile memory.]. .Iadd.SRAM .Iaddend.cell according to claim 10 wherein said first and second vertically extending bit lines and said first and second vertically extending Vcc lines are all formed from a single conductive layer. 
     
     
       12. An integrated circuit .[.nonvolatile memory.]. .Iadd.SRAM .Iaddend.cell according to claim 11 wherein said single conductive layer is a single metal layer. 
     
     
       13. A conductive pattern for an integrated circuit .[.nonvolatile memory.]. .Iadd.SRAM .Iaddend.cell which is formed in a semiconductor substrate, said conductive pattern comprising: first and second Y-shaped gate conductors on said semiconductor substrate, said Y-shaped gate conductors being nested within one another, said Y-shaped conductors including vertically extending spaced apart main body portions, horizontal arm portions a respective one of which extends from one of the main body portions towards the other of the main body portions, and vertical arm portions a respective one of which extends from the respective horizontal arm portion away from the other horizontal arm portion; and   a horizontally extending word line on said semiconductor substrate.   
     
     
       14. A conductive pattern according to claim 13 wherein said first and second Y-shaped conductors and said horizontally extending word line are all formed from a first conductive layer. 
     
     
       15. A conductive pattern according to claim 14 further comprising first and second vertically extending interconnection lines, located between said vertically extending spaced apart main body portions of said Y-shaped gate conductors, and a horizontally extending Vss conductor which overlies said horizontally extending word line. 
     
     
       16. A conductive pattern according to claim 15 wherein said first and second vertically extending interconnection lines and said horizontally extending Vss conductor are all formed from a second conductive layer. 
     
     
       17. A conductive pattern according to claim 16 further comprising first and second vertically extending bit lines, a respective one of which overlies a respective one of said vertically extending interconnection lines, and first and second vertically extending Vcc lines, located outside of said first and second vertically extending bit lines. 
     
     
       18. A conductive pattern according to claim 15 wherein said first and second bit lines and said first and second Vcc lines are all formed from a third conductive layer. 
     
     
       19. A conductive pattern according to claim 18 wherein said first and second conductive layers are first and second polyslicon layers, and wherein said third conductive layer is a metal layer.