Packaging for semiconductor logic devices

Abstract

A logic module design is disclosed which incorporates an unencapsulated wafer section or sections. The disclosed module is an improvement over previous designs in that it is less expensive and easier to manufacture due to the reduced number of components and the complexity of the components, is faster and consumes less power because of its shorter trace lengths and smaller size, and is more reliable as a result of its greatly reduced number of interconnects.

We claim: 
     
       1. A memory module for receiving information from, and transferring information to, an electronic device in a plurality of parallel processes, the plurality of parallel processes being addressed as a byte of said information, comprising: a. a wafer section having a substantially planar surface, die attach locations, plural memory arrays, and plural data out signals, with one data out signal corresponding to each memory array;   b. a plurality of conductive leads, said leads being self-supporting for connection of said wafer section to an external device without the benefit of supporting encapsulation material, said leads further being electrically coupled with said wafer section die attach locations thereby providing an electrical pathway allowing the transfer of said logic information between said wafer section and the electronic device, said pathway providing channels between said wafer section and the electronic device, said wafer section thereby addressable in byte data segments; and   c. said plurality of conductive leads and said wafer section forming a module which has a substantially flat profile, which extends planarly in a direction generally defined by said planar surface of said wafer section.   
     
     
       2. The memory module of claim 1, further comprising an optically opaque layer superimposed over said wafer section. 
     
     
       3. The memory module of claim 1, wherein one of said data out signals has been deselected, and said corresponding memory array is inactive. 
     
     
       4. The memory module of claim 1, wherein said wafer section further comprises more than one unsingulated semiconductor die. 
     
     
       5. The memory module of claim 1, wherein said die attach locations are electrically coupled with said conductive leads by flex circuit means, wherein said flex circuit comprises plural internal conductive traces substantially encased in an insulative material. 
     
     
       6. The memory module of claim 5, wherein said traces are coupled with said die attach locations by solder means. 
     
     
       7. The memory module of claim 5, wherein said solder comprises gold. 
     
     
       8. The memory module of claim 1, wherein conductive and nonconductive layers are fabricated on the surface of said wafer section subsequent to the fabrication of said die attach locations, said die attach locations being electrically coupled with one or more of said conductive layers and said conductive leads are electrically coupled with one or more of said conductive layers. 
     
     
       9. The memory module of claim 1, wherein said wafer section is free from any substantially supporting encapsulation material. 
     
     
       10. The memory module of claim 1, wherein said wafer section is substantially encased in supporting encapsulation material. 
     
     
       11. The memory module of claim 1, further comprising a support member wherein said wafer section is received upon said support member. 
     
     
       12. The memory module of claim 11, further comprising more than one wafer section. 
     
     
       13. The memory module of claim 11, wherein the composition of said support member comprises aluminum.