Semiconductor memory device including memory cells connected to a ground line

Abstract

A memory cell array in a static random access memory (SRAM) includes an improved circuit. Memory cells in one row are connected to a ground line. The memory cells in another row are connected to the ground line. Word lines each are connected alternately to the memory cells of two rows column by column. In a read operation, when one of the word lines is activated, a current flows from the memory cell to the two ground lines. Since a total of currents flowing through one ground line is reduced, the rise of potentials of the ground lines is prevented, so that destruction of data can be prevented.

What is claimed is: 
     
       1. A semiconductor memory device, comprising: a semiconductor substrate;   a memory cell array including a plurality of memory cells disposed in rows and columns on said substrate,   each said memory cell including a field effect transistor on said substrate and being bounded by first and second ground lines in the column direction;   a third ground line formed on the substrate in the row direction and connected to said memory cells; and   a word line formed on said substrate in the row direction and connected to said memory cells,   plural pairs of successive memory cells connected to said word line being positioned alternately in neighboring rows.   
     
     
       2. The semiconductor memory device as recited in claim 1, wherein said third ground line includes a conductive layer formed on said substrate,   said field effect transistor includes active regions formed in said substrate, and   said conductive layer is connected to said active regions in said memory cells.   
     
     
       3. The semiconductor memory device as recited in claim 1, wherein said word line is formed in plural, and neighboring word lines cross each other on said substrate.   
     
     
       4. The semiconductor memory device as recited in claim 3, wherein said neighboring word lines include first and second polysilicon interconnections crossing each other on said substrate.   
     
     
       5. The semiconductor memory device as recited in claim 1, wherein said first and second ground lines include grounded metal interconnections and   said third ground line has one end connected to said first ground line and the other end connected to said second ground line.   
     
     
       6. The semiconductor memory device as recited in claim 2, wherein said conductive layer includes a third polysilicon interconnection formed on said substrate.   
     
     
       7. The semiconductor memory device as recited in claim 1, wherein plural pairs of successive memory cells connected to said word line are positioned alternately column by column in neighboring rows.   
     
     
       8. The semiconductor memory device as recited in claim 1, wherein plural pairs of successive memory cells connected to said word line are positioned alternately two columns by two columns in neighboring rows.   
     
     
       9. The semiconductor memory device as recited in claim 1, wherein said semiconductor memory device is a static random access memory device.   
     
     
       10. A semiconductor memory device, comprising: a semiconductor substrate;   a memory cell array including a plurality of memory cells disposed in rows and columns on said substrate,   each said memory cell being bounded by first and second ground lines in the column direction;   a third ground line formed on said substrate in the row direction and connected to said memory cells; and   a word line formed on said substrate in the row direction and connected to said memory cells,   successive memory cells connected to said word line including memory cells in the odd numbered columns and memory cells in the even numbered columns positioned alternately in neighboring rows.   
     
     
       11. A semiconductor memory device, comprising: a semiconductor substrate;   a memory cell array including a plurality of memory cells disposed in rows and columns on said substrate,   each said memory cell being bounded by first and second ground lines in the column direction;   a word line formed on said substrate in the row direction and connected to said memory cells; and   a third ground line formed on said substrate in the row direction and connected to said memory cells,   plural pairs of successive memory cells connected to said third ground line being positioned alternately in neighboring rows.   
     
     
       12. The semiconductor memory device as recited in claim 11, wherein said third ground line is formed in plural, and neighboring third ground lines cross each other on said substrate.   
     
     
       13. The semiconductor memory device as recited in claim 12, wherein said neighboring third ground lines include first and second conductive layers crossing each other on said substrate.   
     
     
       14. The semiconductor memory device as recited in claim 11, wherein said first and second ground lines include grounded metal interconnections, and   said third ground line has one end connected to said first ground line, and the other end connected to said second ground line.   
     
     
       15. A semiconductor memory device, comprising: a memory cell array including a plurality of memory cells disposed in rows and columns;   a plurality of ground lines each connected to said memory cells in a corresponding row in said memory cell array; and   a plurality of oblique word lines each connected to a corresponding memory cell aligned in a diagonal direction in said memory cell array.   
     
     
       16. The semiconductor memory device according to claim 15, wherein each of said oblique word lines includes a plurality of first conductive layers and a plurality of second conductive layers which are disposed alternately to each other and which are connected in series to each other.   
     
     
       17. A semiconductor memory device, comprising: a semiconductor substrate;   a memory cell array including a plurality of memory cells disposed in rows and columns on said substrate,   each said memory cell being bounded by first and second ground lines in the column direction;   a third ground line formed on said substrate in the row direction and connected to said memory cells;   a word line formed between said first and second ground lines on said substrate in the row direction and connected to said memory cells,   successive memory cells connected to said word line including two successive memory cells at an end portion on the side of said first ground line in the word line positioned alternately in neighboring rows, and two successive memory cells at an end portion on the side of said second ground line in the word line positioned alternately in neighboring rows.   
     
     
       18. A semiconductor memory device, comprising: a semiconductor substrate;   a plurality of memory cells disposed in rows and columns on said substrate,   each said memory cell being bounded by first and second ground lines in the column direction;   first and second word lines formed on said substrate in the row direction and connected to said memory cells; and   a third ground line formed on said substrate in the row direction and connected to said memory cells,   successive memory cells connected to said third ground line including two successive memory cells at an end portion on the side of said first ground line in the third ground line positioned alternately in neighboring rows, and two successive memory cells at an end portion on the side of said second ground line in the third ground line positioned alternately in neighboring rows. .Iadd.   
     
     
       19.  A semiconductor memory device including two adjacent memory cells, comprising: a semiconductor substrate;   a first conductive layer formed on said substrate;   a first and a second access transistor, each having a gate formed from said first conductive layer;   a first and a second driver transistor, each having an active region formed in said substrate;   an insulating layer formed on said first and second access transistor gates and said first and second driver transistor active regions, said insulating layer having a first and a second contact hole therein to expose said first and second access transistor gates, respectively, and a third contact hole to expose said first and second driver transistor active regions;   a second conductive layer formed on said insulating layer;   a first and a second word line formed from said second conductive layer, said first word line being connected to said first access transistor gate through said first contact hole, and said second word line being connected to said second access transistor gate through said second contact hole; and   a ground line formed from said second conductive layer, said ground line being connected to said driver transistor active regions through said third contact hole. .Iaddend..Iadd.20. A semiconductor memory device according to claim 19, further comprising:   first and second driver transistor gates, wherein said first and second driver transistor gates are formed perpendicular to said first and second access transistor gates, respectively. .Iaddend..Iadd.21. A semiconductor memory device according to claim 19, further comprising first and second   
     
     
        load elements. .Iaddend..Iadd.22.  A semiconductor memory device according to claim 21, wherein said first and second load elements are PMOS transistors. .Iaddend..Iadd.23. A semiconductor memory device according to claim 19, wherein said first and second access transistor gates are formed from polycide. .Iaddend..Iadd.24. A semiconductor memory device according to claim 20, wherein said first and second driver transistor gates are formed from polycide. .Iaddend..Iadd.25. A semiconductor memory device including a memory cell, comprising: a semiconductor substrate;   a first conductive layer formed on said substrate;   a first and a second access transistor each having a sate formed from said first conductive layer;   a first and a second driver transistor, each having an active region formed in said substrate;   an insulating layer formed on said first and second access transistor gates and said first and second driver transistor active regions;   said insulating layer having a first contact hole therein to expose said first access transistor gate and a second contact hole therein to expose said first driver transistor active region;   a second conductive layer formed on said insulating layer;   a word line formed from said second conductive layer, said word line being connected to said first access transistor gate through said contact hole; and   a ground line formed from said second conductive layer, said ground line being connected to said first driver transistor active region through said   
     
     
        second contact hole. .Iaddend..Iadd.26.  A semiconductor memory device according to claim 25, further comprising: first and second driver transistor gates, wherein said first and second driver transistor gates are formed perpendicular to said first and second access transistor gates, respectively. .Iaddend..Iadd.27. A semiconductor memory device according to claim 25, further comprising first and second load elements. .Iaddend..Iadd.28. A semiconductor memory device according to claim 27, wherein said first and second load elements are PMOS transistors. .Iaddend..Iadd.29. A semiconductor memory device according to claim 25, wherein said first and second access transistor gates are formed from polycide. .Iaddend..Iadd.30. A semiconductor memory device according to claim 26, wherein said first and second driver transistor gates are formed from polycide. .Iaddend..Iadd.31. A semiconductor memory device including a memory cell, comprising:   a semiconductor substrate;   a first polysilicon layer formed on said substrate and acting as an access transistor gate;   a driver transistor having an active region formed in said substrate;   an insulating layer formed on said first polysilicon layer and said driver transistor active region, and having a first contact hole therein to expose said first polysilicon layer and a second contact hole therein to expose said driver transistor active region;   a second polysilicon layer formed on said insulating layer and acting as a word line, said second polysilicon layer being is connected to said first polysilicon layer through said first contact hole; and   a ground line formed from said second polysilicon layer, said ground line being connected to said driver transistor active region through said   
     
     
        second contact hole. .Iaddend..Iadd.32.  The semiconductor memory device according to claim 31, further comprising: another first polysilicon layer formed on said substrate and acting as a driver transistor gate. .Iaddend..Iadd.33. A static random access memory including a memory cell comprising:   a semiconductor substrate;   a first polysilicon layer formed on said substrate and acting as an access transistor gate;   a driver transistor having an active region formed in said substrate;   an insulating layer formed on said first polysilicon layer and said driver transistor active region, and having a first contact hole therein to expose said first polysilicon layer and a second contact hole therein to expose said driver transistor active region;   a second polysilicon layer formed on said insulating layer and acting as a word line, said second polysilicon layer being connected to said first polysilicon layer through said first contact hole; and   a ground line formed from said second polysilicon layer, said ground line being connected to said driver transistor active region through said second contact hole. .Iaddend..Iadd.34. The static random access memory according to claim 33, further comprising:   another first polysilicon layer formed on said substrate and acting as a driver transistor gate. .Iaddend.