Semiconductor memory device

Abstract

The semiconductor memory device comprises a memory array (9) and a data bus line (1) for transferring read and write data between the memory array and an input buffer (IB) and an output buffer (OB) and also transferring an information indicating read or write mode operation. The data bus line transfers the read data as a complement signal having a predetermined amplitude which is smaller than a potential difference between high and low level power source lines (7 and 8, respectively). The predetermined amplitude is defined by a first and a second impedance (2 and 3, respectively) connected between the data bus line and a first and a second power source line (7 and 8), respectively, The first impedance (2) is associated with a first end of the data bus line in the input-output buffer area and the second impedance (3) is associated with a second end of the data bus line in the inner circuit area of the device. The write data is transferred via the data bus line (1) as a complement signal having a larger amplitude than that of read data. The memory array accepts the signal on the data bus line as a write data signal according to its amplitude. The memory array (9) is equipped with a write control gate for detecting the amplitude of the complement signal on the data bus lane (1).

What is claimed is: 
     
       1. A semiconductor memory device comprising: a first memory array;   a first and a second data bus line;   a first circuit means activated at least during a data read mode for connecting said first and second data .Iadd.bus .Iaddend.line to a first power source line with a first impedance;   a second circuit means responsive to data read out of said memory array for connecting one of said first and second data .Iadd.bus .Iaddend.lines to a second power source line with a second impedance, said one of said first and second data .Iadd.bus .Iaddend.lines thereby taking an intermediate level between levels of said first and second power source lines;   a data write means responsive to write data for supplying said first and second data bus lines with true and complementary signals indicative of said write data, a difference in level between said true and complementary signals being close to a difference in level between said first and second power lines; and   a read amplifier coupled to said first and second data .Iadd.bus .Iaddend.lines for amplifying a potential difference therebetween during said data read mode.   
     
     
       2. The semiconductor memory device as claimed in claim 1, wherein said first and second potential levels are a positive voltage level and a ground level, respectively. 
     
     
       3. The semiconductor memory device as claimed in claim 2, further comprising a write control gate circuit coupled between said memory array and said first and second data .Iadd.bus .Iaddend.lines, said write control gate circuit including a logical gate circuit having an input threshold voltage lower than said intermediate level. 
     
     
       4. The semiconductor memory device as claimed in claim 1, wherein said first circuit means include a first and a second transistor each connected between said first power source line and an associated one of said first and second data .Iadd.bus .Iaddend.lines, said second circuit means include a third and a fourth transistor each connected between said second power source line and an associated one of said first and second data .Iadd.bus .Iaddend.lines, and said intermediate level is determined by a ratio of impedance values between said first and said third transistors or said second and fourth transistors. 
     
     
       5. The semiconductor memory device as claimed in claim 4, wherein said data write means cooperates with said first and second transistors to supply said first and second data bus lines with said true and complementary signals indicative of said write data during a data write mode, and said first and second transistors are rendered conductive irrespective of said write data during said data read mode. 
     
     
       6. The semiconductor memory device as claimed in claim 1, further comprising a controller for outputting a first control signal to said second circuit means for a first time period in response to an input of an address data for said memory array, said second circuit means being activated by said first control signal to connect said first and second data bus lines to said second power source line in accordance with said read data during said first time period. 
     
     
       7. The semiconductor memory device as claimed in claim 6, wherein said controller further outputs a second control signal to said read amplifier in response to said input of said address data and in said first time period, said read amplifier being activated by said second control signal to amplify and hold said read data appearing on said first and second data bus lines. 
     
     
       8. The semiconductor memory device as claimed in claim 1, wherein said memory array is divided into a first and a second memory array portions and said second circuit means is divided into a first and a second partial circuits which are provided correspondingly to said first and second memory array portions, and a control circuit for outputting a first control signal to activate said first partial circuit and a second control signal to activate said second partial circuit. 
     
     
       9. The semiconductor memory device as claimed in claim 8, wherein said control circuit outputs each of said first and second control signals as a pulse signal in response to a transition of said address data. 
     
     
       10. The semiconductor memory device as claimed in claim 1, further comprising an activation control circuit for supplying an activation signal to said second circuit means according to an address data for said memory array, said second circuit means thereby being activated to connect said first and second data bus lines to said second power source line in accordance with said read data. 
     
     
       11. A semiconductor memory device comprising: a memory array;   a data bus line;   a read driver coupled between said memory array and said data bus line for driving, in response to read data from said memory array, said data bus line such that said data bus line takes a first voltage level when said read data is a first logic level and a second voltage level when said read data is a second logic level, said first voltage level being different from said second voltage level;   a write driver coupled to said data bus line for driving in response to write data to be supplied to said memory array, said data bus line such that said data bus line takes a third voltage level when said write data is one of said first and second logic levels and a fourth voltage level when said write data is the other of said first and second logic levels, said third voltage level being higher than each of said first and second voltage levels and said fourth voltage level being lower than each of said first and second voltage levels;   a write gate coupled between said memory array and said data bus line for transferring said write data to said memory array.   
     
     
       12. A semiconductor memory device comprising: a memory bank, a data bus line associated with said memory bank for transferring read and write data, said data bus line being equipped with a read circuit block and a write circuit block, said read circuit block driving said data bus line according to said read data from said memory bank to transport a read data signal, said read data signal taking a first voltage level when said read data is a first logic level and a second voltage level when said read data is a second logic level, said first voltage level being different from said second voltage level, and said write circuit block driving said data bus line according to said write data to be supplied to said memory bank to transport a write data signal, said write data signal taking a third voltage level when said write data is one of said first and second logic levels and a fourth voltage level when said write data is the other of said first and second logic levels, said third voltage level being higher than each of said first and second voltage levels and said fourth voltage level being lower than each of said first and second voltage levels. .Iadd.   
     
     
       13.  A semiconductor memory device comprising: a first memory array;   a first and a second data bus line;   a first circuit means activated at least during a data read mode for connecting said first and second data bus line to a first power source line with a first impedance; and   a second circuit means responsive to data read out of said memory array for connecting one of said first and second data bus lines to a second power source line with a second impedance, said one of said first and second data bus lines thereby taking an intermediate level between levels of said first and second power source lines. .Iaddend..Iadd.14. A semiconductor memory device as claimed in claim 13, further comprising a read amplifier coupled to said first and second data bus lines for amplifying a potential difference therebetween during said data read mode. .Iaddend..Iadd.15. A semiconductor memory device as claimed in claim 14, further comprising a data write means responsive to write data for supplying said first and second data bus lines with true and complementary signals indicative of said write data. .Iaddend..Iadd.16. A semiconductor memory device as claimed in claim 13, further comprising a data write means responsive to write data for supplying said first and second data bus lines with true and complementary signals indicative of said write data. .Iaddend..Iadd.17. A semiconductor memory device as claimed in claim 16, wherein a difference in level between said true and complementary signals being close to a difference in level between said first and second power   
     
     
        lines. .Iaddend..Iadd.18.  A semiconductor memory device as claimed in claim 13, wherein said first circuit means includes a first transistor and a second transistor, each connected between said first power source line and an associated one of said first and second data bus lines, said second circuit means includes a third transistor and a fourth transistor each connected between said second power source line and an associated one of said first and second data bus lines. .Iaddend..Iadd.19. A semiconductor memory device as claimed in claim 18, wherein said first transistor and 
     
     
        said second transistor are P-channel transistors. .Iaddend..Iadd.20.  A semiconductor memory device as claimed in claim 18, wherein said third transistor and said fourth transistor are N-channel transistors. 
     
     
        .Iaddend..Iadd.21.  A semiconductor memory device as claimed in claim 20, wherein said intermediate level is determined by a ratio of impedance values between said first transistor and said third transistor or said second transistor and said fourth transistor. .Iaddend..Iadd.22. A semiconductor memory device as claimed in claim 18, wherein said third transistor and said fourth transistor have small size and large impedance so as to drive or discharge said first and second data bus lines to a potential level which is close to the level of said first power source line. .Iaddend..Iadd.23. A semiconductor memory device as claimed in claim 22, wherein said first transistor and said second transistor have a large size relative to the size of said third transistor and said fourth transistor, so as to perform a read operation at high speed with small current consumption. .Iaddend.