Planarized selective tungsten metallization system

Abstract

In an improved selection tungsten metallization system, a plurality of orifices (20) are cut into a first level dielectric layer (18). A nucleation layer (52), preferably Ti-W alloy, is then formed in each orifice (20) and on the outer surface of the first dielectric layer (18) in a second-level metallization pattern. A second dielectric layer (30) is deposited over the first dielectric layer (18) and the nucleation layer (52), and a reverse second level metallization pattern is used to etch slots (58) back down to the nucleation layers (52) and into orifices (20). Thereafter, tungsten is deposited by selective CVD to fill the first level orifices (20) and the second level slots (58) until the upper surfaces (62) of the tungsten conductors (60) are substantially coplanar with the upper surface (38) of the second dielectric layer (30).

What is claimed is: 
     
       1. A process for forming a conductive interconnection in an integrated circuit structure, comprising the steps of: providing a partially formed integrated circuit having a substrate structure;   forming a first .[.thick.]. insulating layer on said substrate; forming at least one contact hole through said insulating layer.Iadd., exposing a portion of said substrate.Iaddend.;   depositing a .[.thin.]. nucleation layer on said first insulating layer.Iadd., wherein said nucleation layer is formed at least on the outer surface of said first insulating layer, the sidewalls of said contact hole and on the exposed portion of said substrate, while leaving at least a portion of said contact hole voided.Iaddend.;   patterning said .[.thin.]. nucleation layer;   forming a second .[.thick.]. insulating layer on said first insulating layer and said patterned .[.thin.]. nucleation layer;   forming an opening in said second insulating layer to expose said patterned .[.thin.]. nucleation layer; and   selectively depositing a conductor in said opening, said patterned .[.thin.]. nucleation layer serving as a nucleation site for said selective deposition.   
     
     
       2. The process of claim 1 wherein said opening in said second insulating layer is formed by etching said second insulating layer, said .[.thin.]. nucleation layer serving as an etch stop for said etching. .[.3. The process of claim 1 further comprising the step of filling said contact hole with a conductive material prior to said depositing of said thin nucleation layer..]..[.4. The process of claim 3 wherein said step of filling said contact hole comprises the steps of: forming a contact nucleation layer of said substrate at the bottom of said contact hole; and   selectively depositing a conductive material in said contact hole using   
     
     
        said contact nucleation layer as a nucleation site..].5. The process of claim .[.3.]. .Iadd.1, .Iaddend.wherein said .[.thin nucleation layer covers the walls of said contact hole and covers the exposed portion of said substrate, said.]. selective deposition fill.[.ing.]..Iadd.s 
     
     
        .Iaddend.said contact hole. 6. The process of claim 1 wherein said .[.thin.]. nucleation layer comprises a Titanium-Tungsten alloy and said 
     
     
        conductor comprises Tungsten. 7. A process for forming a conductive interconnection in an integrated circuit structure, comprising the steps of: providing a partially formed integrated circuit having a substrate structure;   forming a first .[.thick.]. insulating layer on said substrate; depositing a .[.thin.]. nucleation layer on said first insulating layer;   patterning said .[.thin.]. nucleation layer, said patterned nucleation layer having a contact opening exposing said first .[.thick.]. insulating layer for formation of a contact hole;   forming a second .[.thick.]. insulating layer on said first insulating layer and said patterned .[.thin.]. nucleation layer;   forming an etch mask .[.for patterning.]. .Iadd.on .Iaddend.said second insulating layer;   etching said second insulator layer using said etch mask to provide an opening in said second .[.thick.]. insulating layer, said opening exposing .Iadd.at least .Iaddend.said .Iadd.contact opening in said .Iaddend.patterned .[.thin.]. nucleation layer;   forming said contact hole in said first insulating layer using said .[.thin.]. nucleation layer and said etch mask .[.to.]. as a pattern for etching said first insulating layer;   .Iadd.forming a second nucleation layer on said nucleation layer and in said contact hole; .Iaddend.   selectively depositing a conductor in said opening, said patterned .[.thin.]. nucleation layer serving as a nucleation site for said   
     
     
        selective deposition. 8. The process of claim 7 wherein said opening in said second insulating layer is formed by etching said second insulating layer, said .[.thin.]. nucleation layer serving as an etch stop for said 
     
     
        etching. 9. The process of claim 7 wherein said .[.thin.]. nucleation layer comprises a Titanium-Tungsten alloy and said conductor comprises 
     
     
        Tungsten. 10. A process for forming a conductive interconnection in an integrated circuit structure, comprising the steps of: providing a partially formed integrated circuit having a substrate structure;   forming a first .[.thick.]. insulating layer on said substrate; depositing a etch stop layer on said first insulating layer;   patterning said etch stop layer, said patterned etch stop layer having a contact opening exposing said first .[.thick.]. insulating layer for formation of a contact hole;   forming a second .[.thick.]. insulating layer on said first insulating layer and said etch stop layer;   forming an etch mask .[.for patterning.]. .Iadd.on .Iaddend.said second insulating layer;   etching said second insulating layer using said etch mask to provide an opening in said second .[.thick.]. insulating layer, said opening exposing .Iadd.at least .Iaddend.said .Iadd.contact opening in said patterned .Iaddend.etch stop layer;   forming said .[.contact.]. hole in said first insulating layer using said etch stop layer and said etch mask .[.to.]. as a pattern for etching said first insulating layer;   forming a .[.thin.]. nucleation layer on said etch stop layer and in said contact hole; and   selectively depositing a conductor in said opening, said patterned .[.thin.]. nucleation layer serving as a nucleation site for said   
     
     
        selective deposition. 11. The process of claim 10 wherein said opening in said second insulating layer is formed by etching said second insulating 
     
     
        layer, said etch stop layer serving as an etch stop for said etching. 12. The process of claim 10 wherein said .[.thin.]. nucleation layer comprises a Titanium-Tungsten alloy and said conductor comprises Tungsten. .Iadd.13. The process of claim 1, wherein said nucleation layer comprises a bilayer. .Iaddend..Iadd.14. The process of claim 1, wherein said nucleation layer is sufficiently thin to assist in maintaining a substantially planarized upper surface of said second insulating layer. 
     
     
        .Iaddend..Iadd.15.  The process of claim 1, wherein said second insulating layer is sufficiently thick to assist in maintaining a substantially planarized upper surface of said second insulating layer. .Iaddend..Iadd.16. The process of claim 1, wherein said second insulating layer is sufficiently thick and said nucleation layer is sufficiently thin to assist in maintaining a substantially planarized upper surface of said second thick insulating layer. .Iaddend..Iadd.17. The process of claim 1, and further comprising the step of depositing a second nucleation layer on said nucleation layer after said step of forming an opening, such that said second nucleation layer serves as a nucleation site for said selective deposition. .Iaddend..Iadd.18. The process of claim 17, wherein said nucleation layer serves as an etch stop for said step of forming an opening. .Iaddend..Iadd.19. A process for forming a conductive interconnection in an integrated circuit structure, comprising the steps of: forming a first insulating layer on a substrate;   depositing a nucleation layer on said first insulating layer;   patterning said nucleation layer, said patterned nucleation layer having a contact opening exposing said first insulating layer;   forming a second insulating layer on said first insulating layer and said patterned nucleation layer;   forming an opening in said second insulating layer to expose at least said contact opening in said patterned nucleation layer;   forming a hole in said first insulating layer using said nucleation layer and said second insulating layer as a pattern for etching said first insulating layer;   depositing a second nucleation layer on said nucleation layer and in said hole after said step of forming an opening; and   selectively depositing a conductor in said opening, said second nucleation layer serving as a nucleation site for said selective deposition.   
     
     
        .Iaddend..Iadd.20.  A process for forming a conductive interconnection in an integrated circuit structure, comprising the steps of: forming a first insulating layer on a substrate;   depositing an etch stop layer on said first insulating layer;   patterning said etch stop layer, said patterned etch stop layer having a contact opening exposing said first insulating layer;   forming a second insulating layer on said first insulating layer and said patterned etch stop layer;   forming an opening in said second insulating layer to expose at least said contact opening in said patterned etch stop layer;   forming a hole in said first insulating layer using said etch stop layer and said second insulating layer as a pattern for etching said first insulating layer;   depositing a nucleation layer on said etch stop layer after said step of forming an opening; and   selectively depositing a conductor in said opening, said nucleation layer serving as a nucleation site for said selective deposition. .Iaddend..Iadd.21. A process for forming a conductive interconnection in an integrated circuit structure, comprising the steps of:   providing a partially formed integrated circuit having a substrate structure;   forming a first insulating layer above said substrate;   forming at least one contact hole through said insulating layer, wherein said contact hole has sidewalls and exposes a portion of said substrate;   depositing a nucleation layer above said first insulating layer, wherein said nucleation layer is formed at least on the outer surface of said first insulating layer, on the sidewalls of said contact hole and on the exposed portion of said substrate, while leaving at least a portion of said contact hole voided;   patterning said nucleation layer;   forming a second insulating layer above said first insulating layer and said patterned nucleation layer;   forming an opening in said second insulating layer to expose said patterned nucleation layer; and   selectively depositing a conductor in said opening, said nucleation layer serving as a nucleation site for said selective deposition.   
     
     
        .Iaddend..Iadd.2.  A process for forming a conductive interconnection in an integrated circuit structure, comprising the steps of: providing a partially formed integrated circuit having a substrate structure;   forming a first insulating layer on said substrate;   forming at least one contact hole through said insulating layer, wherein said contact hole has sidewalls and exposes a portion of said substrate;   depositing a nucleation layer on said first insulating layer, wherein said nucleation layer is formed at least on the outer surface of said first insulating layer, on the sidewalls of said contact hole and on the exposed portion of said substrate, while leaving at least a portion of said contact hole voided;   patterning said nucleation layer;   forming a second insulating layer above said first insulating layer and said patterned nucleation layer;   forming an opening in said second insulating layer to expose said patterned nucleation layer; and   selectively depositing a conductor in said opening, said nucleation layer serving as a nucleation site for said selective deposition. .Iaddend..Iadd.23. The process of claim 22, wherein said nucleation layer is sufficiently thin to assist in maintaining a substantially planarized   
     
     
        upper surface of said second insulating layer. .Iaddend..Iadd.24.  The process of claim 22, wherein said second insulating layer is sufficiently thick to assist in maintaining a substantially planarized upper surface of said second insulating layer. .Iaddend..Iadd.25. The process of claim 22, wherein said second insulating layer is sufficiently thick and said nucleation layer is sufficiently thin to assist in maintaining a substantially planarized upper surface of said second insulating layer. .Iaddend..Iadd.26. A process for forming a conductive interconnection in an integrated circuit structure comprising the steps of: providing a partially formed integrated circuit having a substrate structure;   forming a first insulating layer above a substrate;   forming at least one contact hole through said insulating layer, wherein said contact hole has sidewalls and exposes a portion of said substrate;   depositing a nucleation layer above said first insulating layer, wherein said nucleation layer is formed at least on the outer surface of said first insulating layer, on the sidewalls of said contact hole and on the exposed portion of said substrate, while leaving at least a portion of said contact hole voided;   patterning said nucleation layer;   forming a second insulating layer above said first insulating layer and said patterned nucleation layer; and   forming an opening in said second insulating layer to expose said patterned nucleation layer; and   selectively depositing a conductor in said opening, said patterned nucleation layer serving as a nucleation site for said selective deposition. .Iaddend..Iadd.27. A process for forming a conductive interconnection in an integrated circuit structure comprising the steps of:   forming a first insulating layer above a substrate;   depositing a nucleation layer above said first insulating layer;   i patterning said nucleation layer, said patterned nucleation layer having a contact opening exposing said first insulating layer;   forming a second insulating layer above said first insulating layer and said patterned nucleation layer; and   forming an opening in said second insulating layer to expose at least said contact opening in said patterned nucleation layer;   i forming a hole in said first insulating layer using said patterned nucleation layer and said second insulating layer as a pattern for etching said first insulating layer;   depositing a nucleation layer on said patterned nucleation layer and in said hole and after said step of forming an opening; and   selectively depositing a conductor in said opening, said patterned nucleation layer serving as a nucleation site for said selective   
     
     
        deposition. .Iaddend..Iadd.28.  A process for forming a conductive interconnection in an integrated circuit structure, comprising the steps of: providing a partially formed integrated circuit having a substrate structure;   forming a first insulating layer on said substrate;   forming at least one contact hole through said insulating layer, wherein said contact hole has sidewalls and exposes a portion of said substrate;   depositing a first nucleation layer on said first insulating layer, wherein said nucleation layer is formed at least on the outer surface of said first insulting layer, on the sidewalls of said contact hole and on the exposed portion of said substrate, while leaving at least a portion of said connection hole voided;   patterning said first nucleation layer;   forming a second insulating layer on said first insulating layer and said patterned first nucleation layer;   forming an opening in said second insulating layer to expose said patterned first nucleation layer;   depositing a second nucleation layer on said first nucleation layer after said step of forming an opening; and   selectively depositing a conductor in said opening, said second nucleation layer serving as a nucleation site for said selective deposition. .Iaddend.