Method for plating using nested plating buses and semiconductor device having the same

Abstract

Routing density of a wiring substrate (10) is increased by providing a nested plating bus (18) as a supplement to an external plating bus (16). A first group of conductive traces (14) is connected to the nested plating bus, while another group of traces is connected to the external plating bus. After the conductive elements are plated, the nested plating bus is removed by etching, milling, or stamping techniques. Use of a nested plating bus increases I/O count for a given substrate area and/or reduces the need to have routing on more than one layer of the substrate.

What is claimed is: 
     
       1. A method for plating a plurality of radially arranged conductive members, wherein each conductive member has an inner end and an outer end and wherein the plurality of conductive members is divided into a first group of conductive members and a second group of conductive members, comprising the steps of: connecting the outer end of each member of the first group to an outer plating bus;   connecting the inner end of each member of the second group to a nested plating bus that is inside the outer plating bus, without connecting the outer end of each member of the second group to the outer plating bus; and   plating the plurality of conductive members.   
     
     
       2. The method of claim 1 wherein the plurality of conductive members comprise a plurality of conductive traces on a surface of a printed wiring substrate. 
     
     
       3. The method of claim 2 wherein the printed wiring substrate has a plurality of bonding fingers for wire bonding to a semiconductor die, and wherein the inner end of each member of the first group is connected to a corresponding bonding finger, and the outer end of each member of the second group is connected to a different corresponding bonding finger than the corresponding bonding finger of each member of the first group. 
     
     
       4. The method of claim 3 wherein the plurality of bonding fingers divides the plurality of conductive members into the first and the second groups of conductive members. 
     
     
       5. A method for plating a wiring substrate comprising the steps of: providing an insulating substrate material having .[.a surface,.]. a package receiving area, and a die receiving area within the package receiving area;   forming an outer plating bus on .[.the surface of.]. the substrate .[.which.]., .Iadd.wherein the outer plating bus .Iaddend.substantially surrounds the package receiving area;   forming a nested plating bus on .[.the surface of.]. the substrate and within the outer plating bus;   forming a first plurality of conductive traces on .[.the surface of.]. the substrate and within the package receiving area, the first plurality of traces being connected to the outer plating bus;   forming a second plurality of conductive traces on .[.the surface of.]. the substrate and within the package receiving area, the second plurality of traces being connected to the outer plating bus; and   plating the first and the second pluralities of conductive traces.   
     
     
       6. The method of claim 5 wherein the first and second pluralities of conductive traces are physically separated from one another by a plurality of conductive bonding fingers formed on the .[.the surface of.]. the substrate and substantially surrounding the die receiving area. 
     
     
       7. The method of claim 5 wherein the steps of forming the outer plating bus, the nested plating bus, the first plurality of conductive traces, and the second plurality of conductive traces are accomplished simultaneously. 
     
     
       8. The method of claim 5 wherein the outer plating bus and the nested plating bus are both substantially rectangular rings. 
     
     
       9. The method of claim 5 further comprising the step of removing the nested plating bus from within the package receiving area to form a plurality of plating stubs. 
     
     
       10. The method of claim 9 wherein the step of removing the nested plating bus comprises chemically etching the nested plating bus. 
     
     
       11. The method of claim 9 wherein the step of removing the nested plating bus comprises mechanically removing the nested plating bus. 
     
     
       12. The method of claim 5 wherein the nested plating bus is formed within the die receiving area of the substrate. 
     
     
       13. A method for making a semiconductor device comprising the steps of: providing a wiring substrate made in accordance with a method comprising the steps of: providing an insulating substrate material having .[.a surface,.]. a package receiving area, and a die receiving area within the package receiving area;   forming an outer plating bus on .[.the surface of.]. the substrate which substantially surrounds the package receiving area;   forming a nested plating bus on .[.the surface of.]. the substrate and within the outer plating bus;   forming a first plurality of conductive traces on .[.the surface of.]. the substrate and within the package receiving area, the first plurality of traces being connected to the outer plating bus;   forming a second plurality of conductive traces on .[.the surface of.]. the substrate and within the package receiving area, the second plurality of traces being connected to the nested plating bus without being connected to the outer plating bus;   plating the first and the second pluralities of conductive traces; and   removing the nested plating bus from the .[.surface of the.]. substrate, leaving a plurality of plating stubs on the .[.surface.]. .Iadd.substrate;.Iaddend.   providing a semiconductor die;   positioning the die within the die receiving area;   electrically coupling the die to the first and the second pluralities of conductive traces; and   encapsulating the die in a protective body.     
     
     
       14. The method of claim 13 wherein the step of positioning the die comprises positioning the die over the plurality of plating stubs. 
     
     
       15. The method of claim 13 further comprising the step of excising the package receiving area of the substrate from remaining portions of the substrate. 
     
     
       16. A semiconductor device comprising: a printed wiring substrate having a periphery, a surface, a die receiving area on the surface, a plurality of conductive bonding fingers formed on the surface and surrounding the die receiving area, a first plurality of conductive vias extending through the substrate and positioned within the plurality of conductive bonding fingers, a second plurality of conductive vias extending through the substrate and positioned without the plurality of conductive bonding fingers, wherein each via of the first and the second pluralities of vias has two associated trace portions on the .[.surface.]. .Iadd.substrate, .Iaddend.a bonding trace portion and a plating trace portion, wherein the bonding trace portion of each via of the first and the second pluralities of vias is routed to a corresponding bonding finger, and wherein the plating trace portion of each via in the second plurality of vias is routed outward to the periphery of the substrate while the plating trace portion of each via in the first plurality of vias is routed inward toward a center of the substrate;   a semiconductor die positioned within the die receiving area;   means for electrically coupling the die to the plurality of bonding fingers on the substrate; and   a protective body encapsulating the semiconductor.   
     
     
       17. The semiconductor device of claim 16 further comprising a recessed portion in .[.the surface of.]. the substrate within the plurality of bonding fingers, and wherein the plating trace portion of each via in the second plurality of vias terminates at the recessed portion. 
     
     
       18. The semiconductor device of claim 16 wherein the printed wiring substrate is selected from a group consisting of: a printed circuit board and a ceramic substrate. 
     
     
       19. A semiconductor device comprising: a printed wiring substrate having a periphery, .[.a surface,.]. a die receiving area on the .[.surface.]. .Iadd.substrate, .Iaddend.a first and a second plurality of conductive vias extending through the substrate, and a plating trace connected to each via of the first and the second pluralities of vias, wherein the plating traces associated with the first plurality of vias exist on the .[.surface.]. .Iadd.substrate .Iaddend.and terminate at the periphery of the substrate and the plating traces associated with the second plurality of vias exist on the .[.surface.]. .Iadd.substrate .Iaddend.and terminate near the die receiving area;   a semiconductor die positioned within the die receiving area;   means for electrically coupling the semiconductor die to the first and the second pluralities of vias; and   means for providing environmental protection to the semiconductor die.   
     
     
       20. The semiconductor device of claim 19 wherein the printed wiring substrate is selected from a group consisting of: a printed circuit board and a ceramic substrate. 
     
     
       21. The semiconductor device of claim 19 further comprising a functional trace associated with each via of the first and the second pluralities of vias for carrying signals to the semiconductor die.