Integration of high performance submicron CMOS and dual-poly non-volatile memory devices using a third polysilicon layer

Abstract

An apparatus and method for integrating a submicron CMOS device and a non-volatile memory, wherein a thermal oxide layer is formed over a semiconductor substrate and a two layered polysilicon non-volatile memory device formed thereon. A portion of the thermal oxide is removed by etching, a thin gate oxide and a third layer of polysilicon having a submicron depth is deposited onto the etched region. The layer of polysilicon is used as the gate for the submicron CMOS device. In so doing a submicron CMOS device may be formed without subjecting the device to the significant re-oxidation required in formation processes for dual poly non-volatile memory devices such as EPROMs and EEPROMs, and separate device optimization is achieved.

We claim: 
     
       1. A method for forming .Iadd.each of a plurality of non-volatile memory cells in an array of such cells, each of said non-volatile memory cells including .Iaddend.a submicron .Iadd.CMOS .Iaddend.transistor adjacent to a non-volatile memory .Iadd.floating-gate .Iaddend.transistor.Iadd., said method .Iaddend.comprising the steps of: (.Iadd.a) .Iaddend.providing a semiconductor substrate of a first conductivity type.[.,.].;   (.Iadd.b) .Iaddend.forming a non-volatile memory .Iadd.floating-gate .Iaddend.transistor on a first region of said semiconductor substrate.[.,.].; including (.Iadd.i) .Iaddend.forming a first gate oxide layer on said substrate,   (.Iadd.ii) .Iaddend.forming a first polysilicon layer on said first gate oxide layer,   (.Iadd.iii) .Iaddend.forming a second gate oxide layer on said .Iadd.first .Iaddend.polysilicon layer,   (.Iadd.iv) forming a second polysilicon layer on said second gate oxide layer,.Iaddend.   (.Iadd.v) .Iaddend.selectively etching said .Iadd.first and second .Iaddend.gate oxide and polysilicon layers to leave a pair of polysilicon gates stacked above a section of said first region, said gates separated from each other by said second gate oxide layer and separated from said substrate by said first gate oxide layer, .Iadd.and .Iaddend.   (.Iadd.vi) .Iaddend.forming doped .Iadd.source and drain .Iaddend.regions of a second conductivity type in said first region proximate to said pair of gates,     (.Iadd.c) .Iaddend.forming a thermal oxide layer over said non-volatile memory .[.device.]. .Iadd.floating-gate transistor .Iaddend.and said semiconductor substrate, .Iadd.said thermal oxide layer being formed to a first thickness which is a predetermined fraction of a desired final thermal oxide thickness, wherein said final thickness is sufficient to withstand a programming voltage of at least 12 volts;.Iaddend.   (.Iadd.d) completely .Iaddend.removing said thermal oxide .Iadd.layer .Iaddend.from a second region of said substrate .Iadd.such that the surface of said second region is left bare.Iaddend., said second region .Iadd.adjacent to but .Iaddend.separated from said first region by a field oxide region.[.,.].;   (.Iadd.e) .Iaddend.forming a third gate oxide layer over said .Iadd.first and .Iaddend.second .[.region.]. .Iadd.regions .Iaddend.of said substrate, .Iadd.said third gate oxide layer being formed to a second thickness such that the sum of said first and second thicknesses is substantially equal to said desired final thermal oxide thickness;.Iaddend.   (.Iadd.f) .Iaddend.forming a third layer of polysilicon over said non-volatile memory .[.device.]. .Iadd.floating-gate transistor .Iaddend.and said third gate oxide layer.[.,.].;   (.Iadd.g) .Iaddend.selectively removing said third layer of polysilicon such that said third layer of polysilicon is removed from everywhere except for atop a portion .Iadd.of .Iaddend.said second region.[.,.].;   (.Iadd.h) .Iaddend.forming a submicron CMOS transistor, including implanting dopants of said second conductivity type into said second region of said substrate adjacent to said portion under said third layer of polysilicon.[.,.]. .Iadd.to form source and drain regions of said submicron CMOS transistor;.Iaddend.   (.Iadd.i) .Iaddend.forming metallized contacts to said submicron CMOS transistor and said non-volatile memory .Iadd.floating-gate .Iaddend.transistor, .Iadd.said contacts coupling the drain of said non-volatile memory floating-gate transistor to the source of said submicron CMOS transistor, coupling the drain of said submicron CMOS transistor to a bitline of the array, coupling the source of said non-volatile memory floating-gate transistor to a ground potential, coupling the third layer of polysilicon forming a control gate of said submicron CMOS transistor to an access line, and coupling the second polysilicon layer forming a control gate of said non-volatile memory floating-gate transistor to a read line, .Iaddend.and   (.Iadd.j) .Iaddend.covering said semiconductor substrate including said submicron CMOS transistor and said non-volatile memory .Iadd.floating-gate .Iaddend.transistor with a protective coating.   
     
     
       2. The method as recited in claim 1 further comprising: oxidizing said pair of .Iadd.polysilicon .Iaddend.gates, prior to forming said thermal oxide layer over said non-volatile memory .[.device.]. .Iadd.floating-gate transistor.Iaddend., whereby charge retention characteristics of said .Iadd.polysilicon .Iaddend.gates are enhanced without impairing performance of said submicron CMOS transistor.   
     
     
       3. The method as recited in claim 1 wherein forming said non-volatile memory .[.trnasistor.]. .Iadd.floating-gate transistor .Iaddend.further comprises the steps of forming an EPROM transistor. 
     
     
       4. The method as recited in claim 1 wherein forming said non-volatile memory .Iadd.floating-gate .Iaddend.transistor further comprises the steps of forming an EEPROM transistor. 
     
     
       5. The method as recited in claim 1 wherein forming said submicron CMOS transistor comprises the steps of forming a submicron CMOS N-channel transistor. 
     
     
       6. The method as recited in claim 1 wherein forming said submicron CMOS transistor comprises the steps of forming a submicron CMOS P-channel transistor. 
     
     
       7. The method as recited in claim 1 wherein said metallized contacts formed to said submicron CMOS transistor are formed contacting said source, drain and gate of said .Iadd.submicron CMOS .Iaddend.transistor. 
     
     
       8. The method as recited in claim 1 wherein said thermal oxide .Iadd.layer .Iaddend.is formed to a depth of approximately 300 angstroms over said non-volatile memory .Iadd.floating-gate .Iaddend.transistor.Iadd., and said third gate oxide layer brings the oxide over said non-volatile memory floating-gate transistor to a desired final thickness of approximately 500 angstroms.Iaddend.. 
     
     
       9. The method as recited in claim 1 wherein said thermal oxide is removed from said first region using a wet HF etch. 
     
     
       10. The method as recited in claim 1 wherein said .Iadd.third .Iaddend.gate oxide layer is formed to a .[.depth.]. .Iadd.thickness .Iaddend.that is less than that of said first gate oxide layer. 
     
     
       11. The method as recited in claim 1 wherein said third gate oxide layer is formed to a depth of between 100 and 150 angstroms. .[.12. The method as recited in claim 1 further including forming a plurality of said non-volatile memory transistors..]..[.13. The method as recited in claim 1 further including forming a plurality of said submicron CMOS 
     
     
        transistors..].14. A method of forming a .Iadd.non-volatile .Iaddend.CMOS memory cell .Iadd.for use in the formation of an array of non-volatile memory cells, said method .Iaddend.comprising: (.Iadd.a) .Iaddend.forming a floating gate CMOS memory transistor .Iadd.in a semiconductor substrate.Iaddend., including (.Iadd.i) .Iaddend.forming a first gate oxide layer on said substrate,   (.Iadd.ii) .Iaddend.forming a first polysilicon layer on said first gate oxide layer,   (.Iadd.iii) .Iaddend.forming a second gate oxide layer on said first polysilicon layer,   (.Iadd.iv) forming a second polysilicon layer on said second gate oxide layer, and.Iaddend.   (.Iadd.v) selectively .Iaddend.etching said .Iadd.first and second .Iaddend.polysilicon layers and said .Iadd.first and second .Iaddend.gate oxide layers to leave a stack of said layers atop said substrate between a .Iadd.first .Iaddend.source region and a .Iadd.first .Iaddend.drain region,     (.Iadd.b) .Iaddend.subsequently forming a high performance CMOS transistor adjacent to said memory transistor, including (.Iadd.i) .Iaddend.forming a third gate oxide .Iadd.on a completely bare region of a surface of .Iaddend.layer on said substrate .Iadd.that is adjacent to but .Iaddend.spaced apart from said .Iadd.floating gate CMOS .Iaddend.memory transistor by a field oxide region, .Iadd.said third gate oxide layer also being formed over said floating gate CMOS memory transistor,.Iaddend.   (.Iadd.ii) .Iaddend.forming a third polysilicon layer on said third gate oxide layer,   (.Iadd.iii) selectively .Iaddend.etching said third polysilicon layer to leave a submicron gate separated from said .Iadd.floating gate CMOS .Iaddend.memory transistor by a field oxide region, and   (.Iadd.iv) .Iaddend.doping said substrate proximate to said submicron gate .Iadd.to form a second source region and a second drain region.Iaddend., and     (.Iadd.c) forming metallized contacts coupling said second source region to said first drain region .Iaddend.such that said high performance .Iadd.CMOS .Iaddend.transistor can electrically communicate with said   
     
     
        .Iadd.floating gate CMOS .Iaddend.memory transistor. 15. In a method of forming a .Iadd.non-volatile .Iaddend.CMOS memory cell with a three-layer polysilicon process, the improvement comprising: (.Iadd.a) .Iaddend.forming a floating gate CMOS memory transistor in a first time interval, including (.Iadd.i) .Iaddend.forming a first gate oxide layer on a substrate,   (.Iadd.ii) .Iaddend.forming a first polysilicon layer on said first gate oxide layer,   (.Iadd.iii) .Iaddend.forming a second gate oxide layer on said first polysilicon layer,   (.Iadd.iv) .Iaddend.forming a second polysilicon layer on said second gate oxide layer, .Iadd.and.Iaddend.   (.Iadd.v) selectively .Iaddend.etching said .Iadd.first and second .Iaddend.polysilicon and gate oxide layers to leave a sense gate disposed above a floating gate disposed above a channel between a source region and a drain region of said substrate, .[.and.].     (.Iadd.b) .Iaddend.forming a high performance CMOS transistor in a second time interval, after the first time interval, including (.Iadd.i) .Iaddend.forming a third gate oxide layer on a .Iadd.bare .Iaddend.section of said substrate adjacent to said .Iadd.floating gate CMOS .Iaddend.memory transistor, said section separated from said .Iadd.floating gate CMOS .Iaddend.memory .[.cell.]. .Iadd.transistor .Iaddend.by a field oxide region,   (.Iadd.ii) .Iaddend.forming a third polysilicon layer on said third gate oxide layer,   (.Iadd.iii) selectively .Iaddend.etching said third polysilicon layer to leave a gate atop said section, and   (.Iadd.iv) .Iaddend.doping said section around said gate to form electrically conductive regions, .Iadd.and.Iaddend.     (.Iadd.c) forming metallic contacts coupling one of said electrically conductive regions of said high performance CMOS transistor to said drain region of said floating gate CMOS memory transistor .Iaddend.such that said high performance .Iadd.CMOS .Iaddend.transistor can electrically communicate with said .Iadd.floating gate CMOS .Iaddend.memory transistor.