Structure of contact between wiring layers in semiconductor integrated circuit device

Abstract

An insulation film is interposed between a first-level wiring layer and a second-level wiring layer. A contact hole is formed in the insulation film on the first-level wiring layer to electrically connect the first-level wiring layer and second-level wiring layer. The contact hole is larger than the width of the first-level wiring layer and second-level wiring layer. The second-level wiring layer is formed on a side wall and a bottom portion of the contact hole and electrically connected to the first-level wiring layer.

What is claimed is: 
     
       1. A semiconductor device comprising: a first-level wiring layer;   a first insulating film formed on said first-level wiring layer;   a contact hole formed in said first insulating film to expose a portion of said first-level wiring layer; and   a second-level wiring layer electrically connected to said first-level wiring layer by an open box-shaped contact formed in said contact bole, said second-level wiring layer including a first portion formed on said first insulating film and connected to a first sidewall portion of said open box-shaped contact, and a second portion formed on said first insulating film and connected to a second sidewall portion of said open-box-shaped contact.   
     
     
       2. The semiconductor device according to claim 1, wherein said first-level wiring layer is formed on a second insulating film. 
     
     
       3. The semiconductor device according to claim 1, further comprising a third insulating film which is formed in the opening of said open box-shaped contact. 
     
     
       4. The semiconductor device according to claim 1, wherein said first-level wiring layer is formed to extend in a first direction, said second-level wiring layer is formed to extend in a second direction so as to intersect said first-level wiring layer, and said open box-shaped contact is formed at the intersection of said first-level wiring layer and said second-level wiring layer. 
     
     
       5. The semiconductor device according to claim 1, wherein said first-level wiring layer and said second-level wiring layer are formed to extend parallel with each other, and said open box-shaped contact is formed at an overlapping portion of said first-level wiring layer and said second-level wiring layer. 
     
     
       6. A semiconductor device comprising: a plurality of first-level wiring layers formed in a first direction and in parallel with one another;   a plurality of second-level wiring layers formed in a second direction perpendicular to the first direction and in parallel with one another;   a first insulation film interposed between said plurality of first-level wiring layers and said plurality of second-level wiring layers; and   a contact hole formed in a portion of said first insulation film at at least one intersection of said plurality of first-level wiring layers and said plurality of second-level wiring layers, to a depth reaching an upper surface of said first-level wiring layer, a side of said contact hole parallel with the first direction being longer than a width of said second-level wiring layer and shorter than a length two times an interval between said plurality of second-level wiring layers plus the width of said second-level wiring layer, a side of said contact hole parallel with the second direction being longer than a width of said first-level wiring layer and shorter than a length two times an interval between said plurality of first-level wiring layers plus the width of said first-level wiring layer, and said second-level wiring layer being formed at least on a side wall and a bottom portion of said contact hole, thereby electrically connecting said second-level wiring layer to said first-level wiring layer at the bottom portion of said contact hole.   
     
     
       7. The semiconductor device according to claim 6, wherein said plurality of first-level wiring layers are formed on a second insulation film. 
     
     
       8. The semiconductor device according to claim 6, further comprising a third insulation film which is buried in said second-level wiring layer in said contact hole. 
     
     
       9. The semiconductor device according to claim 6, wherein said second-level wiring layer is formed by filling said contact hole. 
     
     
       10. A semiconductor device comprising: a plurality of first-level wiring layers formed in parallel with one another;   a plurality of second-level wiring layers formed in parallel with one another along said plurality of first-level wiring layers;   a first insulation film interposed between said plurality of first-level wiring layers and said plurality of second-level wiring layers; and   a contact hole formed in a portion of said first insulation film at at least one overlap portion of said plurality of first-level wiring layers and said plurality of second-level wiring layers, to a depth reaching an upper surface of said first-level wiring layer, a side of said contact hole perpendicular to said plurality of first-level wiring layers and said plurality of second level wiring layers being longer than a width of said plurality of first-level wiring layers and said plurality of second-level wiring layers and shorter than a length two times an interval between said plurality of first-level wiring layers and said plurality of second-level wiring layers plus the width of said plurality of first-level wiring layers and said plurality of second-level wiring layers, and said second-level wiring layer being formed at least on a side wall and a bottom portion of said contact hole, thereby electrically connecting said second-level wiring layer to said first-level wiring layer at the bottom portion of said contact hole.   
     
     
       11. The semiconductor device according to claim 10, wherein said plurality of first-level wiring layers are formed on a second insulation film. 
     
     
       12. The semiconductor device according to claim 10, further comprising a third insulation film which is buried in said second-level wiring layer in said contact hole. 
     
     
       13. The semiconductor device according to claim 10, wherein said second-level wiring layer is formed by filling said contact hole. 
     
     
       14. A semiconductor device comprising: element isolation films formed on a semiconductor substrate;   a plurality of gate electrodes formed on a surface of said semiconductor substrate through a gate insulation film and connected to a word line;   source/drain regions formed in said semiconductor substrate on sides of said plurality of gate electrodes;   an insulation film coating said source/drain regions;   a contact hole formed in said insulation film above one of said source/drain regions so as to include part of said plurality of gate electrodes and part of said element isolation film;   a bit line connected to the one of said source/drain regions and coating a side wall and a bottom of said contact hole, a width of said bit line on said insulation film being smaller than a diameter of said contact hole; and   a capacitor electrically connected to another of said source/drain regions.   
     
     
       15. The semiconductor device according to claim 14, wherein an upper surface of said source/drain regions is higher in level than an upper surface of said element isolation film, and a depth of said source/drain regions is greater than that of a step portion formed by a difference in level between the upper surface of said source/drain regions and the upper surface of said element isolation film. 
     
     
       16. The semiconductor device according to claim 14, wherein an upper surface of said source/drain regions is higher in level than an upper surface of said element isolation film, a depth of said source/drain regions is smaller than that of a step portion formed by a difference in level between the upper surface of said source/drain regions and the upper surface of said element isolation film, and said source/drain regions extend onto a side wall of the step portion. 
     
     
       17. The semiconductor device according to claim 1, wherein a size of said contact hole in a direction parallel to a width of said first-level wiring layer is larger than the width of said first-level wiring layer. 
     
     
       18. The semiconductor device according to claim 1, wherein said open box-shaped contact is part of said second wiring layer. 
     
     
       19. A semiconductor device, comprising: a first conductive layer;   an insulating layer formed on said first conductive layer;   a second conductive layer formed on said insulating layer; and   a contact formed in a contact hole in said insulating layer for electrically connecting said first conductive layer and said second conductive layer, a size of said contact hole in a direction parallel to a width of said first conductive layer being greater than the width of said first conductive layer and a size of said contact hole in a direction parallel to a width of said second conductive layer being greater than the width of said second conductive layer.   
     
     
       20. The semiconductor device according to claim 19, wherein said first conductive layer comprises a first wiring layer and said second conductive layer comprises a second wiring layer. 
     
     
       21. The semiconductor device according to claim 20, wherein said contact fills said contact hole. 
     
     
       22. The semiconductor device according to claim 20, wherein said contact comprises a first wall in contact with said second conducting layer and a second wall in contact with said insulating layer, said first and second walls defining an open interior region therebetween. 
     
     
       23. The semiconductor device according to claim 22, wherein said second wiring layer includes a first portion connected to a first portion of said second wall and a second portion connected to a second portion of said second wall. 
     
     
       24. The semiconductor device according to claim 21, wherein said second wall comprises four wall portions. 
     
     
       25. The semiconductor device according to claim 24, wherein said four wall portions comprise first and second pairs of opposed wall portions. 
     
     
       26. The semiconductor device according to claim 20, wherein said first wiring layer is perpendicular to said second wiring layer. 
     
     
       27. The semiconductor device according to claim 20, wherein said first wiring layer is parallel to said second wiring layer. 
     
     
       28. The semiconductor device according to claim 20, wherein the width of said first wiring layer is W1 and the dimension of said contact hole in a direction parallel to the width of said first wiring layer is W1+2Δα, where Δα is a mask alignment margin for forming said contact. 
     
     
       29. The semiconductor device according to claim 20, wherein the width of said second wiring layer is W2 and the dimension of said contact hole in a direction parallel to the width of said second wiring layer is W2+2Δα, where Δα is a mask alignment margin for forming said contact. 
     
     
       30. The semiconductor device according to claim 19, wherein said first conductive layer is a diffusion region. 
     
     
       31. A semiconductor device, comprising: a semiconductor substrate;   a memory cell formed on said semiconductor substrate, said memory cell comprising: a switching transistor comprising source and drain regions formed in said semiconductor substrate and spaced apart by a channel region and a gate electrode insulatively spaced from said channel region; and   a capacitor electrically connected to one of said source and drain regions;     an insulating layer formed over said source and drain regions; and   a bit line electrically connected to the other of said source and drain regions by a bit line contact formed in a contact hole in said insulating layer, a dimension of said contact hole in a direction parallel to a width of said bit line being greater than the width of said bit line.   
     
     
       32. The semiconductor device according to claim 31, wherein said capacitor is a trench cell capacitor. 
     
     
       33. The semiconductor device according to claim 31, wherein said bit line contact fills said contact hole. 
     
     
       34. The semiconductor device according to claim 31, wherein said bit line contact comprises a first wall in contact with the other of said source and drain regions and a second wall in contact with said insulating layer, said first and second walls deforming an open interior region therebetween. 
     
     
       35. A semiconductor device, comprising: first wiring layers each having a width D and formed with a spacing D therebetween;   an insulating layer formed on said first wiring layers;   second wiring layers each having a width D and formed on said insulating film with a spacing D therebetween; and   a contact formed in a contact hole in said insulating layer for electrically connecting one of said first wiring layers and one of said second wiring layers, a dimension of said contact hole in a direction parallel to the width D of said one first wiring layer being D+2Δα and a dimension of said contact hole in a direction parallel to the width D of said one second wiring layer being D+2Δα, where Δα is an alignment margin for forming said contact.   
     
     
       36. The semiconductor device according to claim 35, wherein said contact fills said contact hole. 
     
     
       37. The semiconductor device according to claim 35, wherein said contact comprises a first wall in contact with said second conducting layer and a second wall in contact with said insulating layer, said first and second walls defining an open interior region therebetween. .Iadd. 
     
     
       38.  A semiconductor device comprising: a semiconductor substrate having a first conductivity type;   a diffusion region formed in said semiconductor substrate, said diffusion region having a second conductivity type and serving as a source/drain region of a memory cell of a DRAM;   a first insulating layer formed on said semiconductor substrate;   a conductive layer formed on said first insulating layer; and   a contact formed in a contact hole in said first insulating layer for electrically connecting said diffusion region and said conductive layer, a size of said contact hole in a direction parallel to the width of said diffusion region being greater than the width of said diffusion region..Iaddend..Iadd.39. The semiconductor device according to claim 38, wherein a bottom portion of said contact is formed at least partly on a second insulating layer..Iaddend..Iadd.40. The semiconductor device according to claim 38, wherein said conductive layer is a bit line..Iaddend..Iadd.41. The semiconductor device according to claim 38, wherein said contact fills said contact hole..Iaddend..Iadd.42. The semiconductor device according to claim 38, wherein said contact comprises a first wall portion in contact with said conductive layer and second wall portions in contact with said first insulating layer..Iaddend..Iadd.43. The semiconductor device according to claim 42, wherein said conductive layer includes a first portion connected to one of said first wall portions and a second portion connected to another one of said first wall portions..Iaddend..Iadd.44. The semiconductor device according to claim 42, wherein said first wall portions comprise two wall portions..Iaddend..Iadd.45. The semiconductor device according to claim 44, wherein said two wall portions comprise a pair of opposed wall portions..Iaddend..Iadd.46. A semiconductor device comprising:   an element isolation film formed on a semiconductor substrate;   a plurality of gate electrodes formed on a surface of said semiconductor substrate through a gate insulation film and connected to a word line;   source/drain regions formed in said semiconductor substrate on sides of said plurality of gate electrodes;   an insulation film coating said source/drain regions and said element isolation film;   a contact hole formed in said insulation film above one of said source/drain regions so as to include part of one of said plurality of gate electrodes and part of said element isolation film;   a bit line formed on said insulation film, and continuously extending over side walls of said contact hole and over a bottom portion of said contact hole including said one of said source/drain regions and said part of said element isolation film, a width of that part of said bit line which is located over said bottom portion of said contact hole being greater than a width of said one of said source/drain regions; and   a capacitor electrically connected to the other of said source/drain regions..Iaddend..Iadd.47. The semiconductor device according to claim 46, wherein said semiconductor substrate, said one of said source/drain regions, another one of said source/drain regions, said one of said plurality of gate electrodes, and said gate insulating film constitute a selection MOS transistor, and said selection MOS transistor and said capacitor constitute a memory cell of a DRAM..Iaddend..Iadd.48. A semiconductor device comprising:   a semiconductor substrate;   an element isolation film formed on a surface portion of said semiconductor substrate;   a DRAM cell formed on said semiconductor substrate, said DRAM cell comprising: a switching transistor comprising a gate electrode formed on said semiconductor substrate, and source and drain regions formed in said semiconductor substrate;   a capacitor electrically connected to one of said source and drain regions;     an insulating layer formed over said switching transistor; and   a bit line continuously extending on part of said insulating layer, in a contact hole formed in said insulating layer, and on part of said element isolation film, said bit line electrically connected to the other of said source and drain regions..Iaddend..Iadd.49. The semiconductor device according to claim 48, wherein said bit line contact fills said contact hole..Iaddend..Iadd.50. The semiconductor device according to claim 48, wherein said bit line contact comprises a first wall in contact with the other of said source and drain regions and a second wall in contact with said insulating layer, said first and second walls defining an open   
     
     
        interior region therebetween..Iaddend..Iadd.51.  A semiconductor device comprising: a first-level layer formed on a semiconductor substrate;   an insulating film formed on said first-level layer;   a contact hole formed in said insulating film; and   a second-level layer formed on said insulating film and at least on a bottom portion and sidewalls of said contact hole and electrically connected to said first-level layer through said contact hole, said second-level layer having a first portion covering the bottom portion and the sidewalls of said contact hole to a height below a top surface of said insulating film and second portions integrally connecting said first portion and a third portion of said second-level layer on the top surface of said insulating film, thereby covering the entire height of the sidewalls of said contact hole where said third portion of said second-level layer extends into said contact hole, wherein said contact hole is wider than said second-level layer..Iaddend.