One time programmable fully-testable programmable logic device with zero power and anti-fuse cell architecture

Abstract

There is a zero power programmable logic device with a one time programmable and fully-testable anti-fuse cell architecture. Specifically, a half-latch and fuse cell circuit allows the PLD to use "zero power" during the standby period since the sense amps are not used to maintain the programmed logic. Additionally, the PLD is capable of being tested for logic gate and logic path integrity, and anti-fuse electrical parameters without permanently programming the anti-fuse.

What is claimed and desired to be secured by United States Patent is: .[. 
     
       1.  A programmable logic device, comprising: a sense amp (10);   a programmable cells (20a) connected to the sense amp, having: a) a half latch circuit (30), wherein the output (31) from the half latch circuit is used to program various portions of the programmable logic device; and   b) a fuse cell circuit (29), coupled to the half latch circuit, for setting the output of the half latch circuit to a high or low signal level..]..[.2. The programmable logic device of claim 1, wherein said half latch circuit comprises:     a power rail (Vcc 37); and   a first (32) and second (34) P-channel transistor, each having the source electrically coupled to the power rail, and the drains coupled   
     
     
        together..]..[.3.  The programmable logic device of claim 2, wherein the half latch circuit further comprises: an inverter having electrical inputs from the drains of the first and second P-channel transistors, and having the output electrically coupled to the gate of the second P-channel transistor, the output of the inverter is the output of the half latch circuit for setting a state for various   
     
     
        portions of the programmable logic device..].4. .[.The programmable logic device of claim 3,.]. .Iadd.A programmable logic device, comprising: a sense amp;   a programmable cell (20a) connected to the sense amp having: a) a half latch circuit (30), wherein the output (31) from the half latch circuit is used to program various portions of the programmable logic device, .Iaddend.wherein .[.the.]. .Iadd.said .Iaddend.half latch circuit .[.further.]. comprises: a power rail (V cc  37);   a first (32) and second (34) P-channel transistor, each having the source electrically coupled to the power rail, and the drains coupled together;   an inverter having electrical inputs from the drains of the first and second P-channel transistors, and having the output electrically coupled to the gate of the second P-channel transistor, the output of the inverter is the output of the half latch circuit for setting a state for various portions of the programmable logic device; and   a third P-channel transistor (38) having its source electrically coupled to the drains of the first and second P-channel transistors.Iadd.; and     b) a fuse cell circuit (29), coupled to the half latch circuit, for setting the output of the half latch circuit to a high or low signal     
     
     
        level.Iaddend.. 5. The programmable logic device of claim 4, wherein said fuse cell circuit comprises: a first N-channel transistor (42) having the drain electrically coupled to the source of the third P-channel transistor; and   an anti-fuse cell (44) having: a) an input coupled to a digit line (11) which is coupled to the sense amp; and   b) an output electrically coupled to the source of the first N-channel     
     
     
        transistor (42). 6. The programmable logic device of claim 5, further comprising: a second N-channel transistor (40) having the source coupled to the first N-channel transistor (42) and the third P-channel transistor (38), and its drain coupled to ground. .[.7. A PLD programming circuit, comprising:   an output line (31);   fuse circuit means (29), electrically coupled to the output line, having a low state for pulling the voltage of the first node down, and having a high state for maintaining the voltage on the first node; and   latching circuit means (30), coupled to the line, having a first mode for outputting a high signal to the output line while the fuse circuit means is in a low state, and a second mode for outputting a low signal to the   
     
     
        output line while the fuse circuit means is in a high state..].8. .[.The PLD of claim 7,.]. .Iadd.A PLD programming circuit, comprising: a first node (35);   an output line (31) connected to the first node of the PLD programming circuit;   fuse circuit means (29), electrically coupled to the output line, having a low state for pulling the voltage of the first node down, and having a high state for maintaining the voltage on the first node, .Iaddend.wherein the fuse circuit means comprises: .[.a.]. .Iadd.the .Iaddend.first node (35), coupled between the fuse circuit and the half latch circuit;   a digit line (11); .Iadd.and .Iaddend.   an anti-fuse (44), coupled between the digit line and the first node (35), for enabling the high state on the first node when the anti-fuse is unprogrammed, and enabling the low state on the first node when the anti-fuse is programmed.Iadd.; and     latching circuit means (30) coupled to the output line of the PLD programming circuit, having a first mode for outputting a high signal to the output line while the fuse circuit means is in a low state, and a second mode for outputting a low signal to the output line of the PLD programming circuit while the fuse circuit means is in a high   
     
     
        state.Iaddend.. 9. The PLD of claim .[.6.]..Iadd.8.Iaddend., further comprising: a protection circuit (42), coupled between the first node and the   
     
     
        anti-fuse, for inhibiting the anti-fuse from breaking down over time. 10. The PLD of claim 9, further comprising: a program transistor (40) for selectively enabling current through the   
     
     
        anti-fuse during programming of the anti-fuse. 11. The programmable logic device of claims .[.1.]..Iadd.4.Iaddend., wherein the sense amp uses no power during operating periods of the programmable   
     
     
        logic device. 12. The PLD programming circuit of claim .[.7.]..Iadd.8.Iaddend., further comprising: a) a programmable cell including the fuse circuit means and the latching circuit means;   b) a sense amp electrically coupled to the programmable cell; and   c) the sense amp using no power during operating periods of the PLD. .Iadd.13. A semiconductor device having a normal operating period, said semiconductor device comprising:   a sense amp requiring no power during said normal operating period of the semiconductor device;   at least one programmable cell connected to the sense amp, the programmable cell including: a half latch circuit, wherein the output from the half latch circuit used to program portions of the semiconductor device wherein the half latch circuit comprises: a power rail;   a first and second P-channel transistors each having the source thereof connected to the power rail and the drains thereof connected;   an inverter having electrical inputs from the drains of the first and second P-channel transistors, and having the output connected to the gate of the second P-channel transistor, the output of the inverter is the output of the half latch circuit for setting a state for various portions of the semiconductor device; and   a third P-channel transistor having its source connected to the drains of the first and second P-channel transistors; and       at least one fuse cell circuit coupled to the half latch circuit for setting the output of the half latch circuit to a high or low signal level, the fuse cell circuit including: a first transistor; and   an anti-fuse..Iaddend..Iadd.14. The semiconductor device of claim 13, wherein said fuse cell circuit comprises:     the first transistor comprising a first N-channel transistor having the drain electrically coupled to the source of the third P-channel transistor; and   the antifuse comprising an anti-fuse having: an input connected to a digit line which is coupled to the sense amp; and   an output connected to the source of the first N-channel transistor..Iaddend..Iadd.15. The semiconductor device of claim 13, further comprising:     a second N-channel transistor having the source thereof connected to the first N-channel transistor and the third P-channel transistor having the   
     
     
        drain thereof connected to ground..Iaddend..Iadd.16.  A circuit for a semiconductor device having periods of operation, said circuit comprising: a first node;   an output line connected to the first node;   a fuse circuit connected to the first node, the fuse circuit having a first state for pulling the voltage of the first node down and having a second state for maintaining the voltage on the first node, the fuse circuit including: a digit line; and   an anti-fuse having an unprogrammed state and a programmed state, the anti-fuse connected between the digit line and the first node enabling the second state on the first node when the anti-fuse is in the unprogrammed state; and     a latching circuit connected to the first node, the latching circuit having a first mode for outputting a high signal to the output line while the fuse circuit is in the first state and a second mode for outputting a low signal to the output line while the fuse circuit is in the second state..Iaddend..Iadd.17. The circuit of claim 16, wherein the fuse circuit comprises:   the first node connected between the fuse circuit and the latching circuit..Iaddend..Iadd.18. The circuit of claim 17, further comprising:   a protection circuit connected between the first node and the anti-fuse inhibiting the anti-fuse from breaking down over time..Iaddend..Iadd.19. The circuit of claim 18, further comprising:   a program transistor selectively enabling current through the anti-fuse during programming of the anti-fuse to the programmed state. .Iadd.20. The circuit of claim 14, wherein the first state of the fuse circuit includes a low state..Iaddend..Iadd.21. The circuit of claim 16, wherein the second state of the fuse circuit includes a high state..Iaddend..Iadd.22. The circuit of claim 16, said circuit further comprising:   the first node being connected between the fuse circuit and half latch circuit and connected to the output line;   a digit line; and   an anti-fuse having a unprogrammed state and programmed state, the anti-fuse connected between the digit line and the first node enabling the second state of the fuse circuit on the first node when the anti-fuse is unprogrammed and enabling the first state on the first node when the   
     
     
        anti-fuse is programmed..Iaddend..Iadd.23.  The circuit of claim 16, said circuit further comprising: a programmable cell including the fuse circuit and the latching circuit; and   a sense amp connected to the fuse circuit using no power during said period of operation of said semiconductor device..Iaddend..Iadd.24. A circuit for a semiconductor device having periods of operation, said circuit comprising:   a digit line;   a sense amp connected to the digit line, the sense amp using no power during said operating periods of said semiconductor device;   a first node;   an output line connected to the first node; and   a programmable cell including a fuse circuit connected to the digit line and the first node and a latching circuit connected to the first node and the output line..Iaddend..Iadd.25. The circuit of claim 24, wherein the programmable cell of said circuit further comprising:   the fuse circuit having a first state for pulling the voltage of the first node down and having a second state for maintaining the voltage on the first node; and   the latching circuit having a first mode for outputting a high signal to the output line while the fuse circuit is in the first state and a second mode for outputting a low signal to the output line while the fuse circuit is in the second state..Iaddend..Iadd.26. The circuit of claim 24, wherein the first state of the fuse circuit includes a low   
     
     
        state..Iaddend..Iadd.     The circuit of claim 24, wherein the second state of the fuse circuit includes a high state..Iaddend..Iadd.28. The circuit of claim 24, wherein the first state of the fuse circuit includes a low state and wherein the second state of the fuse circuit includes a high state..Iaddend..Iadd.29. The circuit of claim 24, said circuit further comprising: the first node being connected between the fuse circuit and latching circuit and connected to the output line; and   the fuse circuit including an anti-fuse having an unprogrammed state and programmed state, the anti-fuse connected between the digit line and the first node enabling the second state of the fuse circuit on the first node when the anti-fuse is unprogrammed and enabling the first state on the first node when the anti-fuse is programmed..Iaddend..Iadd.30. The circuit of claim 24, wherein the fuse circuit of said circuit further comprising:   an anti-fuse having a unprogrammed state and programmed state, the anti-fuse connected between the digit line and the first node enabling the second state of the fuse circuit on the first node when the anti-fuse is unprogrammed and enabling the first state on the first node when the   
     
     
        anti-fuse is programmed..Iaddend..Iadd.31.  A circuit for a semiconductor device having periods of operation, said circuit comprising: an output line;   a first node connected to the output line;   a sense amp using no power during at least one of said operating periods of said semiconductor device; and   a programmable cell including a fuse circuit and latching circuit, the first node connected between the fuse circuit and the latching circuit, wherein the fuse circuit is connected to the output line, the fuse circuit having a first state for pulling the voltage of the first node down and having a second state for maintaining the voltage on the first node, the fuse circuit including: a digit line; and   an anti-fuse having an un programmed state and a programmed state, the anti-fuse connected between the digit line and the first node, the unprogrammed state of the anti-fuse enabling the second state on the first node and the programmed state of the anti-fuse enabling the first state on the first node when the anti-fuse is programmed;      and   wherein the latching circuit is connected to the output line, the latching circuit having a first mode for outputting a high signal to the output line while the fuse circuit is in the first state and a second mode for outputting a low signal to the output line while the fuse circuit is in a     
     
     
        second state..Iaddend..Iadd.32.  The circuit of claim 31, wherein the first state of the fuse circuit includes a low state..Iaddend..Iadd.33. The circuit of claim 31, wherein the second state of the fuse circuit includes a high state..Iaddend..Iadd.34. The circuit of claim 31, wherein the first state of the fuse circuit includes a low state and wherein the second state of the fuse circuit includes a high state..Iaddend..Iadd.35. A circuit for a semiconductor device having periods of operation, at least one of said periods of operation being a standby period of operation, said circuit comprising: an output line;   a first node connected to the output line;   a sense amp using no power during said standby period of operation of said semiconductor device; and   a programmable cell including a fuse circuit and latching circuit, the first node connected between the fuse circuit and the latching circuit, wherein the fuse circuit is connected to the output line, the fuse circuit having a first state for pulling the voltage of the first node down and having a second state for maintaining the voltage on the first node, the fuse circuit including: a digit line; and   an anti-fuse having an un programmed state and a programmed state, the anti-fuse connected between the digit line and the first node, the unprogrammed state of the anti-fuse enabling the second state on the first node and the programmed state of the anti-fuse enabling the first state on the first node when the anti-fuse is programmed, the programmed state of the anti-fuse causing no current to be provided from the digit line during said standby period of operation of said semiconductor device;      and   wherein the latching circuit is connected to the output line, the latching circuit having a first mode for outputting a high signal to the output line while the fuse circuit is in the first state and a second mode for outputting a low signal to the output line while the fuse circuit is in a     
     
     
        second state..Iaddend..Iadd.36.  The circuit of claim 35, wherein the first state of the fuse circuit includes a low state..Iaddend..Iadd.37. The circuit of claim 35, wherein the second state of the fuse circuit includes a high state..Iaddend..Iadd.38. The circuit of claim 35, wherein the first state of the fuse circuit includes a low state and wherein the second state of the fuse circuit includes a high state..Iaddend..Iadd.39. A circuit for a semiconductor device having periods of operation, at least one of said periods of operation of said semiconductor device being a standby period, said circuit comprising: an output line;   a first node connected to the output line; and   a programmable cell including a fuse circuit and latching circuit, the first node connected between the fuse circuit and the latching circuit, wherein the fuse circuit is connected to the output line, the fuse circuit having a first state for pulling the voltage of the first node down and having a second state for maintaining the voltage on the first node, the fuse circuit including: a digit line; and   an anti-fuse having an un programmed state and a programmed state, the anti-fuse connected between the digit line and the first node, the unprogrammed state of the anti-fuse enabling the second state on the first node and the programmed state of the anti-fuse enabling the first state on the first node when the anti-fuse is programmed, the programmed state of the anti-fuse causing no current to be provided from the digit line during said standby period of operation of said semiconductor device;      and   wherein the latching circuit is connected to the output line, the latching circuit having a first mode for outputting a high signal to the output line while the fuse circuit is in the first state and a second mode for outputting a low signal to the output line while the fuse circuit is in a second state..Iaddend..Iadd.40. The circuit of claim 39, wherein the first state of the fuse circuit includes a low state..Iaddend..Iadd.41. The circuit of claim 39, wherein the second state of the fuse circuit includes a high state..Iaddend..Iadd.42. The circuit of claim 39, wherein the first state of the fuse circuit includes a low state and wherein the second state of the fuse circuit includes a high state..Iaddend.