Inventor

ZAGAR PAUL S

US58 patents

⚠️ This page may combine multiple inventors who share the name “ZAGAR PAUL S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ZAGAR PAUL S

MICRON TECHNOLOGY INC

Synchronous burst extended data out DRAM

Burst EDO memory device

Optimization circuitry and control for a synchronous memory device with programmable latency period

Burst EDO memory device

Wordline driver circuit having a directly gated pull-down device

Burst EDO memory address counter

Burst EDO memory device address counter

Method for maintaining optimum biasing voltage and standby current levels in a DRAM array having repaired row-to-column shorts

Nonvolatile, zero-power memory cell constructed with capacitor-like antifuses operable at less than power supply voltage

Dynamic random-access memory having a hierarchical data path

Burst EDO memory device

Burst EDO memory device

High speed global row redundancy system

Efficient method for obtaining usable parts from a partially good memory integrated circuit

Circuit for cancelling and replacing redundant elements

Synchronous burst extended data out dram

Efficient method for obtaining usable parts from a partially good memory integrated circuit

Dram wtih open digit lines and array edge reference sensing

Integrated circuit power supply having piecewise linearity

Memory integrated circuits having on-chip topology logic driver, and methods for testing and producing such memory integrated circuits

Field programmable logic array with two or planes

Reduced pitch laser redundancy fuse bank structure

Circuit for cancelling and replacing redundant elements

Efficient method for obtaining usable parts from a partially good memory integrated circuit

Circuit and method for varying a period of an internal control signal during a test mode

DRAM with open digit lines and array edge reference sensing

Circuit and method for varying a period of an internal control signal during a test mode

Local word line phase driver

Method for maintaining optimum biasing voltage and standby current levels in a DRAM array having repaired row-to-column shorts

Circuit for cancelling and replacing redundant elements

Synchronous NAND DRAM architecture

Integrated circuit memory with asymmetric row access topology

CMOS logic cell for high-speed, zero-power programmable array logic devices

One time programmable fully-testable programmable logic device with zero power and anti-fuse cell architecture

Reduced pitch laser redundancy fuse bank structure

Field programmable logic array with speed optimized architecture

Cache memories using DRAM cells with high-speed data path

Local word line phase driver

Circuit and method for varying a period of an internal control signal during a test mode

DRAM cache

Synchronous DRAM cache using write signal to determine single or burst write

Data path for high speed high bandwidth DRAM

Wordline driver circuit having an automatic precharge circuit

DRAM with open digit lines and array edge reference sensing

MICRON SEMICONDUCTOR INC

High speed global row redundancy system

One time programmable fully-testable programmable logic device with zero power and anti-fuse cell architecture

Programmable logic device macrocell with an exclusive feedback and an exclusive external input line for a combinatorial mode and accommodating two separate programmable or planes

(unassigned)

Dynamic random access memory having decoding circuitry for partial memory blocks

Circuit for cancelling and replacing redundant elements

CASPER STEPHEN L

Wordline driver circuit having an automatic precharge circuit