USRE37505EExpiredUtility
Stacked capacitor construction
Est. expiryMar 18, 2012(expired)· nominal 20-yr term from priority
H10D 1/716H10D 1/712H10D 1/042Y10S438/964H10B 12/033H10B 12/31
64
PatentIndex Score
17
Cited by
13
References
83
Claims
Abstract
A method of forming a capacitor on a semiconductor wafer includes: a) in a dry etching reactor, selectively anisotropically dry etching a capacitor contact opening having a minimum selected open dimension into an insulating dielectric layer utilizing selected gas flow rates of a reactive gas component and an inert gas bombarding component, the flow rate of the bombarding component significantly exceeding the flow rate of the reactive component to effectively produce a capacitor contact opening having grooved striated sidewalls and thereby defining female capacitor contact opening striations; b) providing a layer of an electrically conductive storage node material within the striated capacitor contact opening; c) removing at least a portion of the conductive material layer to define an isolated capacitor storage node within the insulating dielectric having striated sidewalls; d) etching the insulating dielectric layer selectively relative to the conductive material sufficiently to expose at least a portion of the external male striated conductive material sidewalls; and e) providing conformal layers of capacitor dielectric and capacitor cell material atop the etched conductive material and over its exposed striated sidewalls. The invention also includes a stacked capacitor construction having an electrically conductive storage node with upwardly rising external sidewalls. Such sidewalls have longitudinally extending striations to maximize surface area and corresponding capacitance in a resulting construction.
Claims
exact text as granted — not AI-modifiedWe claim:
1. A stacked capacitor construction formed within a semiconductor substrate comprising:
an electrically conductive storage node, the storage node having upwardly rising external sidewalls, the upwardly rising external sidewalls having longitudinally extending striations to maximize surface area and corresponding capacitance;
a striated cell dielectric layer provided over the storage node and its associated longitudinally extending striations; and
an electrically conductive striated cell layer provided over the striated cell dielectric layer.
2. The stacked capacitor construction of claim 1 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon.
3. The stacked capacitor construction of claim 1 wherein the electrically conductive material of the cell layer comprises conductively doped polysilicon.
4. The stacked capacitor construction of claim 1 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon, and the electrically conductive material of the cell layer comprises conductively doped polysilicon.
5. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having a striated sidewall;
an electrically conductive storage node formed within the at least one contact opening the storage node having external sidewalls, the external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the external sidewalls including striations;
a dielectric layer provided over the storage node and its associated external sidewalls, the dielectric layer including striations; and
an electrically conductive cell layer provided over the cell dielectric layer, the electrically conductive cell layer including striations.
6. The stacked capacitor construction of claim 5 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon.
7. The stacked capacitor construction of claim 5 wherein the electrically conductive material of the cell layer comprises conductively doped polysilicon.
8. The stacked capacitor construction of claim 5 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon, and the electrically conductive material of the cell layer comprises conductively doped polysilicon.
9. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having a striated sidewall;
an electrically conductive storage node formed within the at least one contact opening, the storage node having rising external sidewalls, the rising external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the rising external sidewalls including striations;
a dielectric layer provided over the storage node and its associated rising external sidewalls, the dielectric layer including striations; and
an electrically conductive cell layer provided over the cell dielectric layer, the electrically conductive cell layer including striations.
10. The stacked capacitor construction of claim 9 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon.
11. The stacked capacitor construction of claim 9 wherein the electrically conductive material of the cell layer comprises conductively doped polysilicon.
12. The stacked capacitor construction of claim 9 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon, and the electrically conductive material of the cell layer comprises conductively doped polysilicon.
13. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having a striated sidewall;
an electrically conductive storage node, the storage node having upwardly rising external sidewalls, the upwardly rising external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the external sidewalls including striations;
a dielectric layer provided over the storage node and its associated upwardly rising sidewalls, the cell dielectric layer including striations; and
an electrically conductive cell layer provided over the cell dielectric layer, the electrically conductive cell layer including striations.
14. The stacked capacitor construction of claim 13 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon.
15. The stacked capacitor construction of claim 13 wherein the electrically conductive material of the cell layer comprises conductively doped polysilicon.
16. The stacked capacitor construction of claim 13 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon and the electrically conductive material of the cell layer comprises conductively doped polysilicon.
17. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having a pretexturized striated sidewall;
an electrically conductive storage node, the storage node having external sidewalls, the external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the external sidewalls including striated sidewalls;
a dielectric layer provided over the storage node and its associated external sidewalls, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, the electrically conductive layer including striations.
18. The stacked capacitor construction of claim 17 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon.
19. The stacked capacitor construction of claim 17 wherein the electrically conductive material of the cell layer comprises conductively doped polysilicon.
20. The stacked capacitor construction of claim 17 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon, and the electrically conductive material of the cell layer comprises conductively doped polysilicon.
21. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having a pretexturized striated sidewall;
an electrically conductive storage node, the storage node having rising external sidewalls, the rising external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the external sidewalls including striations;
a dielectric layer provided over the storage node and its associated rising external sidewalls, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, the electrically conductive layer including striations.
22. The stacked capacitor construction of claim 21 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon.
23. The stacked capacitor construction of claim 21 wherein the electrically conductive material of the cell layer comprises conductively doped polysilicon.
24. The stacked capacitor construction of claim 21 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon, and the electrically conductive material of the cell layer comprises conductively doped polysilicon.
25. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having a pretexturized striated sidewall;
an electrically conductive storage node, the storage node having upwardly rising external sidewalls, the upwardly rising external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the external sidewalls including striations;
a dielectric layer provided over the storage node and its associated upwardly rising external sidewalls, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, the electrically conductive layer including striations.
26. The stacked capacitor construction of claim 25 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon.
27. The stacked capacitor construction of claim 25 wherein the electrically conductive material of the cell layer comprises conductively doped polysilicon.
28. The stacked capacitor construction of claim 25 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon, and the electrically conductive material of the cell layer comprises conductively doped polysilicon.
29. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having a grooved striated sidewall;
an electrically conductive storage node, the storage node having external sidewalls, the external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the external sidewalls including striations;
a dielectric layer provided over the storage node and its associated external sidewalls, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, the electrically conductive layer including striations.
30. The stacked capacitor construction of claim 29 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon.
31. The stacked capacitor construction of claim 29 wherein the electrically conductive material of the cell layer comprises conductively doped polysilicon.
32. The stacked capacitor construction of claim 29 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon, and the electrically conductive material of the cell layer comprises conductively doped polysilicon.
33. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having a grooved striated sidewall;
an electrically conductive storage node, the storage node having rising external sidewalls, the rising external sidewalls each having a surface thereon including to maximize surface area and corresponding capacitance, the surfaces of the external sidewalls including striations;
a dielectric layer provided over the storage node and its associated rising external sidewalls, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, the electrically conductive layer including striations.
34. The stacked capacitor construction of claim 33 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon.
35. The stacked capacitor construction of claim 33 wherein the electrically conductive material of the cell layer comprises conductively doped polysilicon.
36. The stacked capacitor construction of claim 33 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon, and the electrically conductive material of the cell layer comprises conductively doped polysilicon.
37. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having a grooved striated sidewall;
an electrically conductive storage node, the storage node having upwardly rising external sidewalls, the upwardly rising external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the upwardly rising external sidewalls including striations;
a dielectric layer provided over the storage node and its associated upwardly rising sidewalls, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, the electrically conductive layer including striations.
38. The stacked capacitor construction of claim 37 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon.
39. The stacked capacitor construction of claim 37 wherein the electrically conductive material of the cell layer comprises conductively doped polysilicon.
40. The stacked capacitor construction of claim 37 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon, and the electrically conductive material of the cell layer comprises conductively doped polysilicon.
41. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having striations in the sidewall;
an electrically conductive storage node, the storage node having external sidewalls, the external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the external sidewalls including complementary striations therein to the striations in the sidewall of the at least one contact opening of the layer of insulating dielectric material;
a dielectric layer provided over the storage node and its associated external sidewalls; and
an electrically conductive layer provided over the dielectric layer, the electrically conductive layer including striations.
42. The stacked capacitor construction of claim 41 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon.
43. The stacked capacitor construction of claim 41 wherein the electrically conductive material of the cell layer comprises conductively doped polysilicon.
44. The stacked capacitor construction of claim 41 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon and the electrically conductive material of the cell layer comprises conductively doped polysilicon.
45. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having striations in the sidewall;
an electrically conductive storage node, the storage node having rising external sidewalls, the rising external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the rising external sidewalls including complementary striations therein to the striations in the sidewall of the at least one contact opening of the layer of insulating dielectric material;
a dielectric layer provided over the storage node and its associated rising external surfaces, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, the electrically conductive layer including striations.
46. The stacked capacitor construction of claim 45 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon.
47. The stacked capacitor construction of claim 45 wherein the electrically conductive material of the cell layer comprises conductively doped polysilicon.
48. The stacked capacitor construction of claim 45 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon, and the electrically conductive material of the cell layer comprises conductively doped polysilicon.
49. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having striations in the sidewall;
an electrically conductive storage node, the storage node having upwardly rising external sidewalls, the upwardly rising external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the upwardly rising external sidewalls including complementary striations therein to the striations in the sidewall of the at least one contact opening of the layer of insulating dielectric material;
a dielectric layer provided over the storage node and its associated upwardly rising external surfaces, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, the electrically conductive layer including striations.
50. The stacked capacitor construction of claim 49 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon.
51. The stacked capacitor construction of claim 49 wherein the electrically conductive material of the cell layer comprises conductively doped polysilicon.
52. The stacked capacitor construction of claim 49 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon, and the electrically conductive material of the cell layer comprises conductively doped polysilicon.
53. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having striations in the sidewall;
an electrically conductive storage node, the storage node having external sidewalls, the external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the external side walls including striations;
a dielectric layer provided over the storage node and its associated external sidewalls, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, the surface of the electrically conductive layer including partial striations.
54. The stacked capacitor construction of claim 53 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon.
55. The stacked capacitor construction of claim 53 wherein the electrically conductive material of the cell layer comprises conductively doped polysilicon.
56. The stacked capacitor construction of claim 53 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon, and the electrically conductive material of the cell layer comprises conductively doped polysilicon.
57. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having striations in the sidewall;
an electrically conductive storage node, the storage node having raised external sidewalls, the raised external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the raised external sidewalls including striations;
a dielectric layer provided over the storage node and its associated raised external sidewalls, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, the surface of the electrically conductive layer including partial striations.
58. The stacked capacitor construction of claim 57 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon.
59. The stacked capacitor construction of claim 57 wherein the electrically conductive material of the cell layer comprises conductively doped polysilicon.
60. The stacked capacitor construction of claim 57 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon, and the electrically conductive material of the cell layer comprises conductively doped polysilicon.
61. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having striations in the sidewall;
an electrically conductive storage node, the storage node having upwardly raised external sidewalls, the upwardly raised external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the upwardly raised external sidewalls including striations;
a dielectric layer provided over the storage node and its associated upwardly raising external sidewalls, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, the surface of the electrically conductive layer including partial striations.
62. The stacked capacitor construction of claim 61 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon.
63. The stacked capacitor construction of claim 61 wherein the electrically conductive material of the cell layer comprises conductively doped polysilicon.
64. The stacked capacitor construction of claim 61 wherein the electrically conductive material of the storage node comprises conductively doped polysilicon, and the electrically conductive material of the cell layer comprises conductively doped polysilicon.
65. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein;
an electrically conductive storage node formed within the at least one contact opening, the storage node having external sidewalls, the external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the external sidewalls including striations;
a dielectric layer provided over the storage node and its associated external sidewalls, the dielectric layer including striations; and
an electrically conductive cell layer provided over the cell dielectric layer, the electrically conductive cell layer including striations.
66. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein;
an electrically conductive storage node, the storage node having external sidewalls, the external sidewalls each having a texturized surface thereon to maximize surface area and corresponding capacitance, the surfaces of the external side walls including striations;
a dielectric layer provided over the storage node and its associated external sidewalls, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, the surface of the electrically conductive layer including partial striations.
67. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein;
an electrically conductive storage node, the storage node having external sidewalls, the external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the external side walls including striations;
a dielectric layer provided over the storage node and its associated external sidewalls, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, a portion of the surface of the electrically conductive layer including partial striations.
68. A stacked capacitor construction formed within a semiconductor substrate comprising:
an electrically conductive storage node, the storage node having external sidewalls, the external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the external sidewalls including striations;
a dielectric layer provided over the storage node and its associated external sidewalls, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, the surface of the electrically conductive layer including partial striations.
69. The stacked capacitor construction of claim 68 wherein the electrically conductive storage node comprises conductively doped polysilicon.
70. The stacked capacitor construction of claim 68 wherein the electrically conductive layer provided over the dielectric layer comprises conductively doped polysilicon.
71. The stacked capacitor construction of claim 68 wherein the electrically conductive storage node comprises conductively doped polysilicon and the electrically conductive layer provided over the dielectric layer comprises conductively doped polysilicon.
72. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having a minimum selected open contact dimension;
an electrically conductive storage node, the storage node having external sidewalls, the external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the external sidewalls including striations, the electrically conductive storage node having a thickness, the thickness less than about 30 % of the minimum selected open contact dimension of the contact opening in the layer of insulating dielectric material;
a dielectric layer provided over the storage node and its associated external sidewalls, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, the surface of the electrically conductive layer including partial striations.
73. The stacked capacitor construction of claim 72 wherein the electrically conductive storage node comprises conductively doped polysilicon.
74. The stacked capacitor construction of claim 72 wherein the electrically conductive layer provided over the dielectric layer comprises conductively doped polysilicon.
75. The stacked capacitor construction of claim 72 wherein the electrically conductive storage node comprises conductively doped polysilicon and the electrically conductive layer provided over the dielectric layer comprises conductively doped polysilicon.
76. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having a minimum selected open contact dimension;
an electrically conductive storage node, the storage node having external sidewalls, the external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the external sidewalls including striations the electrically conductive storage node having a thickness, the thickness less equal to about 30 % of the minimum selected open contact dimension of the contact opening in the layer of insulating dielectric material;
a dielectric layer provided over the storage node and its associated external sidewalls, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, the surface of the electrically conductive layer including partial striations.
77. The stacked capacitor construction of claim 76 wherein the electrically conductive storage node comprises conductively doped polysilicon.
78. The stacked capacitor construction of claim 76 wherein the electrically conductive layer provided over the dielectric layer comprises conductively doped polysilicon.
79. The stacked capacitor construction of claim 76 wherein the electrically conductive storage node comprises conductively doped polysilicon and the electrically conductive layer provided over the dielectric layer comprises conductively doped polysilicon.
80. A stacked capacitor construction formed within a semiconductor substrate comprising:
a layer of insulating dielectric material located on the semiconductor substrate having at least one contact opening therein, the contact opening having a selected open contact dimension;
an electrically conductive storage node, the storage node having external sidewalls, the external sidewalls each having a surface thereon to maximize surface area and corresponding capacitance, the surfaces of the external sidewalls including striations, the electrically conductive storage node having a thickness, the thickness less than the minimum selected open contact dimension of the contact opening in the layer of insulating dielectric material;
a dielectric layer provided over the storage node and its associated external sidewalls, the dielectric layer including striations; and
an electrically conductive layer provided over the dielectric layer, the surface of the electrically conductive layer including partial striations.
81. The stacked capacitor construction of claim 80 wherein the electrically conductive storage node comprises conductively doped polysilicon.
82. The stacked capacitor construction of claim 80 wherein the electrically conductive layer provided over the dielectric layer comprises conductively doped polysilicon.
83. The stacked capacitor construction of claim 80 wherein the electrically conductive storage node comprises conductively doped polysilicon and the electrically conductive layer provided over the dielectric layer comprises conductively doped polysilicon.Cited by (0)
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