Semiconductor memory device and read and write methods thereof

Abstract

A semiconductor memory device includes input/output circuitry capable of operating in sync with an externally provided I/O clock signal. A data in buffer and a data out buffer provide for serial to parallel conversion of write data and, conversely, parallel to serial conversion of read data. The data buffers can be synchronized with the external I/O clock signal thereby decoupling their operation from the internal system clock signal. This strategy improves I/O bandwidth and further provides for matching different numbers of bit lines or word sizes as between the I/O data port and the memory array itself. An internal I/O clock generator can be provided for generating I/O clock signals, again without the limitation of synchronizing to the internal system clock signal.

What is claimed is:  
     
       1. A semiconductor memory device which includes a plurality of bit lines, a plurality of word lines crossed with said plurality of bit lines, and a memory cell array including a plurality of memory cells positioned at cross points where said bit lines are crossed with said word lines, comprising: 
       an address port for receiving inputs of a row address supplied while a row address enable signal is in a first state and a column address enable signal is in a second state, and a column address supplied while said column address enable signal is in the first state and said row address enable signal is in the second state;  
       a row decoder for receiving the input of said row address from the address port and enabling a word line corresponding to the received row address;  
       a plurality of sense amplifiers for amplifying signals of said bit lines enabled by said memory cells connected to said enabled word line;  
       a column decoder for receiving the input of said column address from the address port and coupling a selected bit line to a common data line; and  
       a source synchronous interface means for interfacing said data common line with the exterior and exchanging data between the exterior of the device and said memory cell array.  
     
     
       2. A semiconductor memory device which includes a plurality of bit lines, a plurality of word lines crossed with said plurality of bit lines, and a memory cell array including a plurality of memory cells positioned at cross points where said bit lines are crossed with said word lines, comprising: 
       an address port for receiving inputs of a row address supplied while a row address enable signal is in a first state and a column address enable signal is in a second state, and a column address supplied while said column address enable signal is in the first state and said row address enable signal is in the second state;  
       a row decoder for receiving the input of said row address from the address port and enabling a word line corresponding to the received row address;  
       a plurality of sense amplifiers for amplifying signals of said bit lines enabled by said memory cells connected to said enabled word line;  
       a column decoder for receiving the input of said column address from the address port and coupling a selected bit line to a common data line; and  
       a source synchronous interface means for interfacing said data common line with the exterior and exchanging data between the exterior of the device and said memory cell array;  
       a row address buffer for receiving said row address and storing said received row address;  
       a column address buffer for receiving said column address and storing said received column address; and  
       a controller  control clock generator for receiving a write enable signal, an address signal,  a column address strobe, a row address strobe, an external clock signal and a chip select signal, for synchronizing said row address and said column address to said external clock, and for storing said synchronized row address and said synchronized column address at said row address buffer and said column address buffer, respectively.  
     
     
       3. A semiconductor memory device which includes a plurality of bit lines, a plurality of word lines crossed with said plurality of bit lines, and a memory cell array including a plurality of memory cells positioned at cross points where said bit lines are crossed with said word lines, comprising: 
       an address port for receiving inputs of a row address supplied while a row address enable signal is in a first state and a column address enable signal is in a second state, and a column address supplied while said column address enable signal is in the first state and said row address enable signal is in the second state;  
       a row decoder for receiving the input of said row address from the address port and enabling a word line corresponding to the received row address;  
       a plurality of sense amplifiers for amplifying signals of said bit lines enabled by said memory cells connected to said enabled word line;  
       a column decoder for receiving the input of said column address from the address port and coupling a selected bit line to a common data line; and  
       a source synchronous interface means for interfacing said data common line with the exterior and exchanging data between the exterior of the device and said memory cell array;  
       wherein said source synchronous interface means is comprised of:  
       a data terminal for receiving data, and  , an I/O clock terminal for a  receiving a source generated synchronous clock signal, and a data output synchronous signal generator, said data terminal and I/O clock terminal arranged for transferring data between the memory device and the exterior;  
       a data-in buffer coupled to the data terminal for receiving sequential data synchronized to said source generated synchronous clock signal, the source generated synchronous signal being provided from the exterior through said I/O clock terminal, and for storing said received sequential data; and  
       a data-out buffer coupled to the data terminal for simultaneously transferring a plurality of output data of said memory cell array in parallel, said transfer being synchronized to a synchronous output signal provided by the data output synchronous signal generator, and for transmitting the output synchronous signal through said data terminal to the exterior 
       a data-out buffer coupled to the data terminal for sequentially transmitting output data through the data terminal to the exterior, and coupled to the I/O clock terminal for transmitting a source synchronous I/O clock signal through the I/O clock terminal to the exterior, wherein the output data and the source synchronous I/O clock signal are responsive to a synchronous output clock signal provided by the data output synchronous signal generator.  
     
     
       4. The device as defined in  claim 3 , wherein said data-out buffer is programmable for selecting a number of bits of output data for said simultaneous transfer  sequential transmission. 
     
     
       5. The device as defined in  claim 3 , wherein said data output synchronous signal generator gates a sequential clock from a clock source equal to or greater than the number of said output data. 
     
     
       6. The device as defined in  claim 3 , wherein said clock  source synchronous I/O clock signal has a frequency greater than that of the internal system clock. 
     
     
       7. The device as defined in  claim 3 , wherein said clock source  data output synchronous signal generator is comprised of a ring oscillator. 
     
     
       8. The device as defined in  claim 7 , wherein said ring oscillator is capable of programming the frequency. 
     
     
       9. A semiconductor memory device which includes a plurality of bit lines, a plurality of word lines crossed with said plurality of bit lines, and a memory cell array including a plurality of memory cells positioned at cross points where said bit lines are crossed with said word lines, comprising: 
       an address port for receiving inputs of a row address supplied while a row address enable signal is in a first state and a column address enable signal is in a second state, and a column address supplied while said column address enable signal is in the first state and said row address enable signal is in the second state;  
       a row decoder for receiving the input of said row address from the address port and enabling a word line corresponding to the received row address;  
       a plurality of sense amplifiers for amplifying signals of said bit lines enabled by said memory cells connected to said enabled word line;  
       a column decoder for receiving the input of said column address from the address port and coupling a selected bit line to a common data line; and  
       a source synchronous interface means for interfacing said data common line with the exterior and exchanging data between the exterior of the device and said memory cell array;  
       wherein said source synchronous interface is comprised of:  
       a data terminal for data, a terminal for a source generation synchronous signal  an I/O clock terminal for a source generated synchronous clock signal, and a data output synchronous signal generator, said terminals being for data exchange;  
       a data-in buffer for receiving more than two sequential data inputted from the exterior transmitted through said terminal for data, at dual edges where said source generation synchronous signal is sequentially transmitted from the exterior through said terminal for said source generation synchronous signal, and storing said received data; and  
       a data-out buffer for simultaneously, transmitting said more than two even sequential output data of said memory cell array, from said dual edges where said data generation synchronous signal is sequentially transmitted from said data output synchronous signal generator, through said terminal for data to the exterior and for transmitting a data output synchronous signal through said terminal for said source generation synchronous signal to the exterior  
       a data-in buffer for receiving more than two sequential data, synchronized to both edges of said source generated synchronous clock signal, said sequential data generated externally and received through said data terminal for data, for receiving the source generated synchronous clock signal that is sequentially transmitted from the exterior through said IO clock terminal, and for storing said sequential data; and  
         a data-out buffer for transmitting more than two sequential output data through said terminal for data to the exterior at both edges of a synchronous output clock signal sequentially provided by said data output synchronous signal generator, for transmitting a source synchronous I/O clock signal through the I/O clock terminal, wherein the sequential output data and the source synchronous I/O clock signal are responsive to the synchronous output clock signal provided by the data output synchronous signal generator .  
     
     
       10. The device as defined in  claim 9 , wherein said data-out buffer is capable of programming the number of said sequential data. 
     
     
       11. The device as defined in  claim 9 , wherein said data output synchronous signal generator gates a sequential clock from a clock source as much as the number of said sequential output data. 
     
     
       12. The device as defined in  claim 9 , wherein said clock source inputs said external clock. 
     
     
       13. The device as defined in  claim 9 , wherein said clock source increases the frequency of said inputted external clock. 
     
     
       14. The device as defined in  claim 9 , wherein said clock source  data output synchronous signal generator is comprised of a ring oscillator. 
     
     
       15. The device as defined in  claim 9 , wherein said ring oscillator is capable of programming the frequency. 
     
     
       16. A method of writing data into a memory array from an external data terminal comprising the steps of: 
       providing an input buffer;  
       receiving an external I/O clock signal;  
       storing a series of input data bits from the data terminal into the input buffer, said storing step including clocking the data bits into the input buffer responsive to the received external I/O clock signal so that said storing step is synchronized to the external I/O clock signal; and  
       transferring a plurality at one time of said stored data bits in parallel from the input buffer into the memory array.  
     
     
       17. A method of writing data into a memory array from an external data terminal comprising the steps of: 
       providing an input buffer;  
       receiving an external I/O clock signal;  
       storing a series of input data bits from the data terminal into the input buffer, said storing step including clocking the data bits into the input buffer responsive to the received external I/O clock signal so that said storing step is synchronized to the external I/O clock signal; and  
       transferring a plurality at one time of said stored data bits in parallel from the input buffer into the memory array;  
       and further comprising partitioning the input buffer into first and second input buffers, both of the first and second input buffers being coupled to the data terminal to receive the input data bits, and coupled to the memory array; and wherein said step of storing a series of input data bits from the data terminal into the input buffer includes:  
       sequentially storing a first series of input data bits into the first input buffer;  
       transferring all of the first series of stored data bits in parallel from the first input buffer into the memory array;  
       sequentially storing a second series of input data bits into the second input buffer;  
       transferring all of the second series of stored data bits in parallel from the second input buffer into the memory array; and  
       repeating said sequentially storing and transferring data steps, alternating between the first and second input buffers, thereby interleaving the input data in the memory array and providing improved setup and hold time of the said steps of transferring the input data into the memory array.  
     
     
       18. The device as defined in  claim 3 , wherein said output data and the source synchronous I/O clock signal have the same phase.  
     
     
       19. A semiconductor memory device which includes a plurality of bit lines, a plurality of word lines crossed with said plurality of bit lines, and a memory cell array including a plurality of memory cells positioned at cross points where said bit lines are crossed with said word lines, comprising: 
       
         an address port for receiving inputs of a row address supplied while a row address enable signal is in a first state and a column address enable signal is in a second state, and a column address supplied while said column address enable signal is in the first state and said row address enable signal is in the second state;  
       
       
         a row decoder for receiving the input of said row address from the address port and enabling a word line corresponding to the received row address;  
       
       
         a plurality of sense amplifiers for amplifying signals of said bit lines enabled by said memory cells connected to said enabled word line;  
       
       
         a column decoder for receiving the input of said column address from the address port and coupling a selected bit line to a common data line; and  
       
       
         a source synchronous interface means for interfacing said data common line with the exterior and exchanging data between the exterior of the device and said memory cell array; wherein said source synchronous interface means is comprised of:  
       
       
         a data terminal for data, an I/O clock terminal for receiving a source generated synchronous clock signal, and a data output synchronous signal generator, said data terminal and I/O clock terminal arranged for transferring data between the memory device and the exterior;  
       
       
         a data-in buffer coupled to the data terminal for receiving data synchronized to said source generated synchronous clock signal, the source generated synchronous signal being provided from the exterior through said I/O clock terminal, and for storing said received sequential data; and  
       
       
         a data-out buffer coupled to the data terminal for transmitting data through the data terminal to the exterior, and coupled to the I/O clock terminal for transmitting a source synchronous I/O clock signal through the I/O clock terminal to the exterior, wherein the data and the source synchronous I/O clock signal are gated by the same internal clock signal that is generated form the data output synchronous signal generator.  
       
     
     
       20. A memory system comprising a memory device, a controller, a clock source that transmits a system clock signal to the memory device and the controller, a plurality of address signal lines, a plurality of control signal lines, a plurality of data bus lines, and a I/O clock signal line, 
       
         wherein the memory device comprises:  
       
       
         a plurality of bit lines, a plurality of word lines crossed with said plurality of bit lines, and a memory cell array including a plurality of memory cells positioned at cross points where said bit lines are crossed with said word lines;  
       
       
         a first plurality of address terminals coupled to the plurality of address signal lines, for receiving a row address when a row address enable signal and a column address enable signal are received in a first state, and for receiving a column address when said column address enable signal and said row address enable signal are received in a second state;  
       
       
         a row decoder for receiving the row address from the address terminals and enabling a word line corresponding to the received row address;  
       
       
         a plurality of sense amplifiers for amplifying signals of said bit lines enabled by said memory cells connected to said enable word lines;  
       
       
         a column decoder for receiving the column address from the address terminals and coupling a selected bit line to a common data line;  
       
       
         a first clock terminal for receiving said system clock signal provided by the clock source;  
       
       
         a first plurality of control terminals coupled to the plurality of control signal lines, for receiving said column address enable signal and said row address enable signal; and  
       
       
         a source synchronous interface means for exchanging data between the memory device and the controller; wherein said source synchronous interface means comprises:  
       
       
         a first plurality of data terminals, coupled to the plurality of data bus lines, for receiving and transmitting data, and a first I/O clock terminal, coupled to the I/O clock signal line, for receiving and transmitting a source synchronous I/O clock signal, wherein said data terminals and I/O clock terminal are arranged for transferring data between the memory device and the controller;  
       
       
         a data output synchronous clock signal generator;  
       
       
         a data-in buffer coupled to the I/O clock terminal for receiving a source synchronous I/O clock signal from the controller, and coupled to the data terminals for receiving sequential data synchronized to the source synchronous I/O clock signal from the controller, and for storing the received sequential data; and  
       
       
         a data-out buffer coupled to the data terminal sequentially transmitting output data to the controller, and coupled to the I/O clock terminal for transmitting a source synchronous I/O clock signal to the controller, wherein the output data and source synchronous I/O clock signal are responsive to a synchronous output clock signal provided by the data output synchronous signal generator;  
       
       
         and wherein the controller comprises:  
       
       
         a second plurality of address terminals coupled to the plurality of address signal lines, and providing address signals to the memory device;  
       
       
         a second clock terminal coupled to the clock source, for receiving said system clock signal provided by the clock source;  
       
       
         a second plurality of control terminals coupled to the plurality of control signal lines, providing said column address enable signal and said row address enable signal to the memory device;  
       
       
         a second plurality of data terminals coupled to the plurality of data lines, for receiving and transmitting said data; and  
       
       
         a second I/O clock terminal coupled to the I/O clock signal line, for receiving and transmitting source generated synchronous clock signals.  
       
     
     
       21. A method of transmitting data from a memory device through a data terminal to the exterior comprising the steps of: 
       
         providing an output buffer and a data output synchronous clock signal generator;  
       
       
         providing a synchronous output clock signal from said data output clock synchronous clock signal generator;  
       
       
         transmitting a source synchronous I/O clock signal responsive to the synchronous output clock signal; and  
       
       
         transmitting output data through the data terminal to the exterior, including clocking the data from the output buffer responsive to the synchronous output clock signal such that the output data is synchronized to the source synchronous I/O clock signal.  
       
     
     
       22. The method of transmitting data as defined in  claim 19 , wherein said output data and source synchronous I/O clock signal are in the same phase.  
     
     
       23. The device as claimed in  claim 5 , wherein said clock source for said data output synchronous signal generator is provided by an external clock generator.  
     
     
       24. The device as defined in  claim 5 , wherein said clock source for said data output synchronous signal generator is generated by an internal clock generator.  
     
     
       25. The device as defined in  claim 9 , wherein said source synchronous I/O clock signal has a frequency greater than that of the internal system clock.  
     
     
       26. The device as defined in  claim 9 , wherein said output data and the source synchronous I/O clock signal are in the same phase.  
     
     
       27. The device as defined in  claim 11 , wherein said clock source for said data output synchronous signal generator is provided by an external clock generator.  
     
     
       28. The device as defined in  claim 11 , wherein said clock source for said data output synchronous signal generator is generated by an internal clock generator.