Inventor

KYUNG KYE-HYUN

KR61 patents

⚠️ This page may combine multiple inventors who share the name “KYUNG KYE-HYUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KYUNG KYE-HYUN

SAMSUNG ELECTRONICS CO LTD

Memory system having point-to-point bus configuration

Devices and methods for controlling active termination resistors in a memory system

Semiconductor memory systems, methods, and devices for controlling active termination

Devices and methods for controlling active termination resistors in a memory system

Repair apparatus and method for semiconductor memory device to be selectively programmed for wafer-level test or post package test

High voltage generating circuit for a semiconductor memory device

Synchronous semiconductor memory device having on-die termination circuit and on-die termination method

Memory system having stub bus configuration

Synchronous semiconductor memory device having on-die termination circuit and on-die termination method

Semiconductor memory device and module for high frequency operation

Memory module device for use in high-frequency operation

Memory system having two-way ring topology and memory device and memory module for ring-topology memory system

Memory system capable of increasing utilization efficiency of semiconductor memory device and method of refreshing the semiconductor memory device

Reference voltage generator and method utilizing clamping

System, device, and method for improved mirror mode operation of a semiconductor memory device

Integrated circuit memory devices that support selective mode register set commands and related methods

Methods of controlling memory modules that support selective mode register set commands

Integrated circuit memory devices that support selective mode register set commands and related memory modules, memory controllers, and methods

Integrated circuit memory devices having data input and output lines extending along the column direction

Integrated circuit devices having a delay locked loop that is configurable for high-frequency operation during test and methods of operating same

Integrated circuit memory devices having direct access mode test capability and methods of testing same

Chip information output circuit

Integrated circuit memory devices including mode registers set using a data input/output bus

Integrated circuit memory devices that support selective mode register set commands

Semiconductor memory device and module for high frequency operation

Semiconductor memory device and method of supplying wordline voltage thereof

Methods of operating memory systems including memory devices set to different operating modes and related systems

Stack package of semiconductor device

Semiconductor memory device having direct sense amplifier implemented in hierarchical input/output line architecture

Mode control circuit for semiconductor device and semiconductor memory device having the mode control circuit

Semiconductor memory device and memory system for improving bus efficiency

Packet type integrated circuit memory devices having pins assigned direct test mode and associated methods

Circuits for testing memory devices having direct access test mode and methods for testing the same

Memory device with prefetched data ordering distributed in prefetched data path logic, circuit, and method of ordering prefetched data

Semiconductor memory device and read and write methods thereof

Input/output circuits and methods for testing integrated circuit memory devices

Integrated circuit memory device including banks of memory cells and related methods

Memory system controlling peak current generation for a plurality of memories by synchronizing internal clock of each memory with a processor clock at different times to avoid peak current generation period overlapping

Synchronous semiconductor memory device having on-die termination circuit and on-die termination method

Devices and methods for controlling active termination resistors in a memory system

Devices and methods for controlling active termination resistors in a memory system

Termination providing apparatus mounted on memory module or socket and memory system using the apparatus

Memory system and semiconductor memory device for enhancing bus efficiency and refresh method of the semiconductor memory device

Integrated circuit memory devices having data input and output lines extending in the column direction, and circuits and methods for repairing faulty cells

Semiconductor device including delay locked loop having periodically activated replica path

Memory devices and methods of operation thereof using interdependent sense amplifier control

Method for receiving data

Method of writing data to a memory

KIM BO-GEUN

Memory system controlling peak current generation for a plurality of memories by monitoring a peak signal to synchronize an internal clock of each memory by a processor clock at different times

KYUNG KYE-HYUN

Devices and methods for controlling active termination resistors in a memory system