Method for receiving data

Abstract

The present invention relates to a synchronous semiconductor memory device with double data rate, and more particularly, to a synchronous semiconductor memory device for inputting and outputting data using a free-running clock and inserting a preamble indicative of start of data into the outputted data. A semiconductor memory device of the present invention receives a data read command from the exterior of the memory device in response to a predetermined clock signal inputted from the exterior, and outputting data including a preamble in response to the clock signal.

What is claimed is: 
     
       1. A semiconductor memory device comprising:
 a memory cell for storing data;   an internal clock generator for generating a first internal clock signal, a second internal clock signal or a third internal clock signal in response to a mode control signal;   a command/address input unit for transferring an externally input command/address signal to inside of the semiconductor memory device in synchronization with the first internal clock signal;   a controller for outputting a plurality of control signals and an address signal in response to the command/address signal so as to control operation of the semiconductor memory device, the controller having a mode register for generating the mode control signal;   a control circuit for selecting between a first mode and a second mode in response to the mode control signal, wherein in the first mode the control circuit selects both of an externally input first clock signal and an externally input second clock signal and in the second mode the control circuit selects only one of the externally input first clock signal and the externally input second clock signal;   a data input unit for receiving data in synchronization with the second internal clock signal;   a data output unit for outputting data including a preamble in synchronization with the third internal clock signal; and   a data processing unit for storing data inputted through the data input unit in the memory cell according to the control signals of the control unit, or transferring the data from the memory cell to the data output unit, wherein the preamble is added to a header of the outputted data and is indicative of start of the data;   wherein:
 in the first mode the internal clock generator generates the first internal clock signal in response to the externally input first clock signal, and generates the second internal clock signal or the third internal clock signal in response to a predetermined control signal and the externally input second clock signal, and 
 in the second mode the internal clock generator generates the first internal clock signal in response to the one of the externally input first clock signal and the externally input second clock signal, and generates the second internal clock signal or the third internal clock signal in response to a predetermined control signal and the one of the externally input first clock signal and the externally input second clock signal. 
   
     
     
       2. The semiconductor memory device of  claim 1 , wherein the preamble added to each data outputted through the data lines has the same level. 
     
     
       3. The semiconductor memory device of  claim 1 , wherein the level of the preamble is a high level. 
     
     
       4. The semiconductor memory device of  claim 1 , wherein the level of the preamble is a low level. 
     
     
       5. The semiconductor memory device of  claim 1 , wherein the preamble added to data outputted through neighboring data lines among the plurality of data lines has different level. 
     
     
       6. The semiconductor memory device of  claim 1 , wherein, in the second mode, the semiconductor memory device generates the first to third internal clock signals using the externally input first clock signal. 
     
     
       7. The semiconductor memory device of  claim 1 , wherein, in the second mode, the semiconductor memory device generates the first to third internal clock signals using the externally input second clock signal. 
     
     
       8. The semiconductor memory device of  claim 1 , wherein if data including the preamble from the outside, the semiconductor memory device detects the preamble included in the input data unit to latch an input data. 
     
     
       9. The semiconductor memory device of  claim 8 , wherein the data input unit further comprises:
 a preamble detecting circuit for latching inputted data including the preamble; and   a data input buffer for inputting an input data in synchronization with the second internal clock signal to the data input unit according to a preamble detection signal from the preamble detection circuit.   
     
     
       10. A semiconductor memory device inputting and outputting data including a preamble, the semiconductor memory device comprising:
 a memory cell for storing data through a plurality of data lines;   an internal clock generator for generating a first internal clock signal, a second internal clock signal or a third internal clock signal in response to a mode control signal;   a command/address input unit for transferring an externally input command/address signal to inside of the semiconductor memory device in synchronization with the internal command/address clock signal;   a controller for outputting a plurality of control signals and an address signal in response to the command/address signal so as to control operation of the semiconductor memory device, the controller having a mode register for generating the mode control signal;   a control circuit for selecting between a first mode and a second mode in response to the mode control signal, wherein in the first mode the control circuit selects both of an externally input first clock signal and an externally input second clock signal and in the second mode the control circuit selects only one of the externally input first clock signal and the externally input second clock signal;   a data input unit for receiving data including a preamble in synchronization with any one of the plurality of internal clock signals;   a data output unit for outputting data including a preamble in synchronization with any one of the plurality of internal clock signals; and   a data processing unit for storing data inputted through the data input unit in the memory cell according to a control signal of the control unit, or transferring the data from the memory cell to the data output unit,   wherein the data output unit comprises a preamble generator for generating the preamble and adding the preamble to the output data, and   wherein:
 in the first mode the internal clock generator generates the first internal clock signal in response to the externally input first clock signal, and generates the second internal clock signal or the third internal clock signal in response to a predetermined control signal and the externally input second clock signal, and 
 in the second mode the internal clock generator generates the first internal clock signal in response to the one of the externally input first clock signal and the externally input second clock signal, and generates the second internal clock signal or the third internal clock signal in response to a predetermined control signal and the one of the externally input first clock signal and the externally input second clock signal. 
   
     
     
       11. The semiconductor memory device of  claim 10 , wherein the data input unit comprises:
 a preamble detector for detecting a preamble of inputted data and generating a preamble detecting signal;   a clock selector for receiving the plurality of internal clock signals and selecting and outputting one of the plurality of internal clock signals in response to the preamble detecting signal; and   a data input buffer for receiving inputted data in synchronization with the internal clock signal selected by the clock selector.   
     
     
       12. The semiconductor memory device of  claim 11 , wherein the plurality of internal clock signals have different phases from each other. 
     
     
       13. The semiconductor memory device of  claim 12 , wherein the plurality of internal clock signals have phase difference of 45°. 
     
     
       14. A method, comprising:
 receiving data at a data input buffer from data terminals that include first and second terminals;   receiving and storing the data from the data input buffer in a memory; and   detecting a preamble received by the data input buffer preceding the data on the data terminals, and which comprises a parallel preamble signal comprising a first logic level on the first terminal and a second logic level, different from the first logic level on the second terminal.    
     
     
       15. The method of claim 14, wherein the data is received from the data terminals which comprise even terminals and odd terminals, the first terminal being an odd terminal, the second terminal being an even terminal, and the preamble is a parallel preamble signal comprising the first logic level on the odd terminals and the second logic level on the even terminals.  
     
     
       16. The method of claim 14, wherein the data is received from the data terminals which comprise even terminals and odd terminals, the first terminal being an odd terminal, the second terminal being an even terminal, and the preamble is a parallel preamble signal comprising the first logic level on the odd terminals and the second logic level on the even terminals during a time period equal to n data input time periods, wherein n is an integer greater or equal to 2.  
     
     
       17. The method of claim 14, wherein the preamble is a parallel preamble signal comprising the first logic level on the first terminal and the second logic level on the second terminal at a first time period and the second logic level on the first terminal and the first logic level on the second terminal at a second time period immediately following the first time period.  
     
     
       18. The method of claim 14, wherein the data is received from the data terminals which comprise even terminals and odd terminals, the first terminal being an odd terminal, the second terminal being an even terminal, and the preamble is a parallel preamble signal comprising the first logic level on the odd terminals and the second logic level on the even terminals at a first time period and the second logic level on the odd terminals and the first logic level on the even terminals at a second time period immediately following the first time period.  
     
     
       19. The method of claim 14, wherein the data is received from the data terminals which comprise first, second, third and fourth terminals, and the preamble is a parallel preamble signal comprising, during a first time period, the first logic level on the first and fourth terminals and the second logic level on the second and third terminals, and during a second time period immediately following the first time period, the first logic level on the first and third terminals and the second logic level on the second and fourth terminals.  
     
     
       20. The method of claim 19, wherein the first, second, third and fourth terminals are nth, nth+1, nth+2 and nth+3 data terminals, respectively.