Method of writing data to a memory

Abstract

The present invention relates to a synchronous semiconductor memory device with double data rate, and more particularly, to a synchronous semiconductor memory device for inputting and outputting data using a free-running clock and inserting a preamble indicative of start of data into the outputted data. A semiconductor memory device of the present invention receives a data read command from the exterior of the memory device in response to a predetermined clock signal inputted from the exterior, and outputting data including a preamble in response to the clock signal.

What is claimed is: 
     
       1. A semiconductor memory device comprising:
 a memory cell for storing data;   an internal clock generator for generating a first internal clock signal, a second internal clock signal or a third internal clock signal in response to a mode control signal;   a command/address input unit for transferring an externally input command/address signal to inside of the semiconductor memory device in synchronization with the first internal clock signal;   a controller for outputting a plurality of control signals and an address signal in response to the command/address signal so as to control operation of the semiconductor memory device, the controller having a mode register for generating the mode control signal;   a control circuit for selecting between a first mode and a second mode in response to the mode control signal, wherein in the first mode the control circuit selects both of an externally input first clock signal and an externally input second clock signal and in the second mode the control circuit selects only one of the externally input first clock signal and the externally input second clock signal;   a data input unit for receiving data in synchronization with the second internal clock signal;   a data output unit for outputting data including a preamble in synchronization with the third internal clock signal; and   a data processing unit for storing data inputted through the data input unit in the memory cell according to the control signals of the control unit, or transferring the data from the memory cell to the data output unit, wherein the preamble is added to a header of the outputted data and is indicative of start of the data;   wherein:
 in the first mode the internal clock generator generates the first internal clock signal in response to the externally input first clock signal, and generates the second internal clock signal or the third internal clock signal in response to a predetermined control signal and the externally input second clock signal, and 
 in the second mode the internal clock generator generates the first internal clock signal in response to the one of the externally input first clock signal and the externally input second clock signal, and generates the second internal clock signal or the third internal clock signal in response to a predetermined control signal and the one of the externally input first clock signal and the externally input second clock signal. 
   
     
     
       2. The semiconductor memory device of  claim 1 , wherein the preamble added to each data outputted through the data lines has the same level. 
     
     
       3. The semiconductor memory device of  claim 1 , wherein the level of the preamble is a high level. 
     
     
       4. The semiconductor memory device of  claim 1 , wherein the level of the preamble is a low level. 
     
     
       5. The semiconductor memory device of  claim 1 , wherein the preamble added to data outputted through neighboring data lines among the plurality of data lines has different level. 
     
     
       6. The semiconductor memory device of  claim 1 , wherein, in the second mode, the semiconductor memory device generates the first to third internal clock signals using the externally input first clock signal. 
     
     
       7. The semiconductor memory device of  claim 1 , wherein, in the second mode, the semiconductor memory device generates the first to third internal clock signals using the externally input second clock signal. 
     
     
       8. The semiconductor memory device of  claim 1 , wherein if data including the preamble from the outside, the semiconductor memory device detects the preamble included in the input data unit to latch an input data. 
     
     
       9. The semiconductor memory device of  claim 8 , wherein the data input unit further comprises:
 a preamble detecting circuit for latching inputted data including the preamble; and   a data input buffer for inputting an input data in synchronization with the second internal clock signal to the data input unit according to a preamble detection signal from the preamble detection circuit.   
     
     
       10. A semiconductor memory device inputting and outputting data including a preamble, the semiconductor memory device comprising:
 a memory cell for storing data through a plurality of data lines;   an internal clock generator for generating a first internal clock signal, a second internal clock signal or a third internal clock signal in response to a mode control signal;   a command/address input unit for transferring an externally input command/address signal to inside of the semiconductor memory device in synchronization with the internal command/address clock signal;   a controller for outputting a plurality of control signals and an address signal in response to the command/address signal so as to control operation of the semiconductor memory device, the controller having a mode register for generating the mode control signal;   a control circuit for selecting between a first mode and a second mode in response to the mode control signal, wherein in the first mode the control circuit selects both of an externally input first clock signal and an externally input second clock signal and in the second mode the control circuit selects only one of the externally input first clock signal and the externally input second clock signal;   a data input unit for receiving data including a preamble in synchronization with any one of the plurality of internal clock signals;   a data output unit for outputting data including a preamble in synchronization with any one of the plurality of internal clock signals; and   a data processing unit for storing data inputted through the data input unit in the memory cell according to a control signal of the control unit, or transferring the data from the memory cell to the data output unit,   wherein the data output unit comprises a preamble generator for generating the preamble and adding the preamble to the output data, and   wherein:
 in the first mode the internal clock generator generates the first internal clock signal in response to the externally input first clock signal, and generates the second internal clock signal or the third internal clock signal in response to a predetermined control signal and the externally input second clock signal, and 
 in the second mode the internal clock generator generates the first internal clock signal in response to the one of the externally input first clock signal and the externally input second clock signal, and generates the second internal clock signal or the third internal clock signal in response to a predetermined control signal and the one of the externally input first clock signal and the externally input second clock signal. 
   
     
     
       11. The semiconductor memory device of  claim 10 , wherein the data input unit comprises:
 a preamble detector for detecting a preamble of inputted data and generating a preamble detecting signal;   a clock selector for receiving the plurality of internal clock signals and selecting and outputting one of the plurality of internal clock signals in response to the preamble detecting signal; and   a data input buffer for receiving inputted data in synchronization with the internal clock signal selected by the clock selector.   
     
     
       12. The semiconductor memory device of  claim 11 , wherein the plurality of internal clock signals have different phases from each other. 
     
     
       13. The semiconductor memory device of  claim 12 , wherein the plurality of internal clock signals have phase difference of 45°. 
     
     
       14. A method of writing data to a memory comprising:
 providing a write command to the memory;   providing a preamble signal to a data terminal of a memory device; and   after providing the preamble signal, providing a data signal to the data terminal, the data signal including a plurality of sequentially provided data bits during respective ones of sequential data output periods to thereby allow writing of data into the memory in accordance with the write command;   wherein the preamble signal is provided over a time period no less than two data output periods, and   wherein the method further comprises providing an address signal to a terminal of the memory device which is separate from all data terminals of the memory device.   
     
     
       15. The method of claim 14, wherein the write command is provided prior to providing the preamble signal. 
     
     
       16. The method of claim 14, further comprising providing the data signal to the data terminal immediately following providing the preamble signal to the data terminal. 
     
     
       17. A method of writing data to a memory comprising:
 receiving a write command in a semiconductor memory device from an external bus;   receiving a preamble signal from a data line of the external bus;   after receiving the preamble signal, receiving a data signal from the data line of the external bus, the data signal including a plurality of sequentially provided data bits received during respective ones of sequential data input periods; and   writing the received data bits to a memory of the semiconductor memory device in accordance with the write command,   wherein the preamble signal is received over a time period no less than two data input periods, and   wherein the method further comprises receiving an address signal from a terminal of the memory device that is separate from all data terminals of the memory device.   
     
     
       18. The method of claim 17, wherein the write command is received prior to providing the preamble signal. 
     
     
       19. The method of claim 17, further comprising receiving the data signal immediately after receiving the preamble signal. 
     
     
       20. The method of claim 17, wherein the data terminals are dedicated to the transmission of data. 
     
     
       21. A method of writing data to a memory comprising:
 receiving a write command in a semiconductor memory device from an external bus;   receiving a preamble signal from a data line of the external bus;   after receiving the preamble signal, receiving a data signal from the data line of the external bus, the data signal including a plurality of sequentially provided data bits received during respective ones of sequential data input periods; and   writing the received data bits to a memory of the semiconductor memory device in accordance with the write command,   wherein the preamble signal is received over a time period no less than two data input periods, and   wherein the method further comprises selecting a clock in response to a detection of the preamble.   
     
     
       22. The method of claim 21, wherein the selecting step includes detecting a timing of the preamble, and selecting one of a plurality of internal clocks based on the detected timing of the preamble. 
     
     
       23. The method of claim 22, wherein the selecting step includes enabling inputs to a circuit internal to the semiconductor memory device upon receipt of an appropriate first portion of the preamble, and then detecting a timing of the preamble by inputting a second portion of the preamble to the circuit. 
     
     
       24. The method of claim 23, wherein the first portion and second portion are provided on different data terminals. 
     
     
       25. The method of claim 21, further comprising detecting a preamble waveform consisting of a logic low voltage signal on plural data terminals. 
     
     
       26. The method of claim 21, further comprising detecting a preamble waveform comprising a logic low signal on at least a first data terminal and a logic low signal on at least a second data terminal. 
     
     
       27. The method of claim 21, further comprising detecting a preamble waveform comprising a logic low signal on odd data terminals and a logic high signal on even data terminals. 
     
     
       28. The method of claim 21, further comprising detecting a preamble waveform consisting of a logic low signal on odd data terminals and a logic high signal on even data terminals. 
     
     
       29. The method of claim 21, further comprising detecting a preamble waveform comprising during a first time period, a logic high signal on odd data terminals and a logic low signal on even data terminals, and during a second time period immediately following the first time period, a logic low signal on odd data terminals and a logic high signal on even data terminals. 
     
     
       30. The method of claim 21, further comprising detecting a preamble waveform comprising during a first time period, a logic high signal on first and fourth data terminals and a logic low signal on second and third data terminals, and during a second time period immediately following the first time period, a logic high signal on first and third data terminals and a logic low signal on second and fourth data terminals. 
     
     
       31. The method of claim 30, further comprising receiving the preamble on the first, second, third and fourth terminals from the nth, nth+1, nth+2 and nth+3 data lines of the external data bus. 
     
     
       32. The method of claim 21, further comprising receiving an address signal from a terminal of the memory device that is separate from all data terminals of the memory device. 
     
     
       33. The method of claim 21, wherein the write command is received prior to providing the preamble signal. 
     
     
       34. The method of claim 21, further comprising receiving the data signal immediately after receiving the preamble signal. 
     
     
       35. The method of claim 21, wherein the data terminals are dedicated to the transmission of data.