Methods for fabricating memory cells and load elements

Abstract

A contact structure provides electrical contact between two polycrystalline silicon interconnect layers. The lower layer has a silicide layer on its upper surface. The upper polycrystalline silicon layer can be doped with a different conductivity type, and makes an ohmic contact with the silicided region of the lower polycrystalline silicon layer.

What is claimed is:  
     
       1. A method for forming a contact in a semiconductor integrated circuit device, comprising the steps of: 
       forming a first polycrystalline silicon interconnect layer having a first conductivity type;  
       forming a silicide layer on the first polycrystalline silicon interconnect layer;  
       forming an insulating layer over the entire device;  
       forming a contact opening in the insulating layer, wherein a contact region on an upper surface of the silicide layer is exposed;  
       forming a second polycrystalline silicon interconnect layer having a second conductivity type over the insulating layer, wherein the second polycrystalline silicon interconnect layer makes ohmic contact with the silicide layer through the contact opening.  
     
     
       2. The method of  claim 1 , wherein the first and second conductivity types are the same type, and wherein the second polycrystalline silicon interconnect layer is lightly doped relative to the first polycrystalline silicon interconnect layer. 
     
     
       3. The method of  claim 1 , wherein the first and second conductivity types are of opposite types. 
     
     
       4. The method of  claim 1 , wherein the first and second conductivity types are the same type, and wherein the first polycrystalline silicon interconnect layer is lightly doped relative to the second polycrystalline silicon interconnect layer. 
     
     
       5. The method of  claim 3 , wherein the first conductivity type is N-type, and the second conductivity type is P-type. 
     
     
       6. The method of  claim 3 , wherein the first conductivity type is P-type, and the second conductivity type is N-type. 
     
     
       7. A method for forming a contact in a semiconductor integrated circuit device, comprising the steps of: 
       forming a first polycrystalline silicon interconnect lyar having a first conductivity type;  
       forming a silicide layer on the first polycrystalline silicon interconnect layer;  
       forming an insulating layer over the entire device;  
       forming a contact opening in the insulating layer, wherein a contact region on an upper surface of the silicide layer is exposed;  
       forming a second polycrystalline silicon interconnect layer having a second conductivity type opposite to the first conductivity type over the insulating layer, wherein the second polycrystalline silicon interconnect layer makes ohmic contact with the silicide layer through the contact opening; and  
       forming a region having the first conductivity type within the second polycrystalline silicon interconnect layer at a location spaced from the contact opening, wherein a P-N junction is formed within the second polycrystalline silicon interconnect layer.  
     
     
       8. A method of fabricating an SRAM cell, comprising the steps of: 
         fabricating first and second driver transistors and first and second pass transistors, said driver transistors each being N - channel field-effect transistors and having respect gates, sources, and drains;    
         connecting said gate of said driver transistor to said drain of second driver transistor, and connecting said gate of said second driver transistor to said drain of said first driver transistor, using a polycide layer comprising a lower polysilicon portion which is doped n - type polysilicon and an upper silicide portion;    
         providing an additional patterned polysilicon layer which includes both heavily doped n - type regions and lightly doped p - type regions,    
         said heavily doped n - regions of said additional polysilicon layer being connected directly to a positive power supply voltage, and    
         said lightly doped p - type regions of said additional polysilicon layer making ohmic contact directly to said silicide portion of said polycide layer to provide pull - up connections to said drains of said driver transistors.   
     
     
       9. A product made by the method of  claim 1 . 
     
     
       10. A product made by the method of  claim 7 . 
     
     
       11. A product made by the method of  claim 8 . 
     
     
       12. The method of  claim 1 , wherein said insulating layer has a thickness in the range of  500 - 1000  Å. 
     
     
       13. The method of  claim 1 , wherein said second polycrystalline silicon interconnect layer includes  10   13    cm   −2    implanted atoms of dopant.   
     
     
       14. The method of  claim 1 , wherein said first polycrystalline silicon interconnect layer includes about  5 × 10   15    cm   −2    implanted atoms of dopant.   
     
     
       15. The method of  claim 7 , wherein the first and second conductivity types are of opposite types. 
     
     
       16. The method of  claim 7 , wherein said insulating layer has a thickness in the range of  500 - 1000  Å. 
     
     
       17. The method of  claim 7 , wherein said second polycrystalline silicon interconnect layer, other than said region having the first conductivity type, includes  10   13    cm   −2    implanted atoms of dopant.   
     
     
       18. The method of  claim 8 , wherein said additional patterned polysilicon layer includes  10   13    cm   −2    implanted atoms of dopant.   
     
     
       19. The method of  claim 8 , wherein said polycide layer includes about  5 × 10   15    cm   −2    implanted atoms of dopant.   
     
     
       20. The method of  claim 8 , wherein said additional patterned polysilicon layer overlies an oxide layer which has a thickness in the range of  500 - 1000  Å.