Content addressable memory (CAM) arrays and cells having low power requirements

Abstract

A content addressable memory (CAM) cell that includes a static random access memory (SRAM) cell that operates in response to a V CC supply voltage. A first set of bit lines coupled to the SRAM cell are used to transfer data values to and from the SRAM cell. The signals transmitted on the first set of bit lines have a signal swing equal to the V CC supply voltage. A second set of bit lines is coupled to receive a comparison data value. The signals transmitted on the second set of bit lines have a signal swing that is less than the V CC supply voltage. For example, the signal swing on the second set of bit lines can be as low as two transistor threshold voltages. The second set of bit lines is biased with a supply voltage that is less than the V CC supply voltage. A sensor circuit is provided for comparing the data value stored in the CAM cell with the comparison data value. The sensor circuit pre-charges a match scan line prior to a compare operation. If the data value stored in the CAM cell does not match the comparison data value, the match sense line is pulled down. The signal swing of the match sense line is smaller than the V CC supply voltage. For example, the signal swing on the match sense line can be as low as one transistor threshold voltage.

1. A content addressable memory (CAM) cell comprising:
 a static random access memory (SRAM) cell that operates in response to a V CC  supply voltage, the SRAM cell storing a data value;  
 a first set of one or more bit lines coupled to the SRAM cell, wherein the data value is written to and read from the SRAM cell on the first set bit lines, the first set of bit lines having a signal swing equal to the V CC  supply voltage; and  
 a second set of bit lines coupled to receive a comparison data value, the second set of bit lines having a signal swing less than the V CC  supply voltage.  
 
     
     
       2. The CAM cell of  claim 1 , further comprising a circuit for comparing the data value with the comparison data value to determine whether a match exists. 
     
     
       3. The CAM cell of  claim 2 , wherein the circuit comprises:
 a first transistor having a gate coupled to receive a signal representative of the data value;  
 and  
 a second transistor having a gate coupled to receive a signal representative of the inverse of the data value.  
 
     
     
       4. The CAM cell of  claim 3 , wherein the second set of bit lines comprises:
 a first bit line coupled to a source region of the first transistor; and  
 a second bit line coupled to a source region of the second transistor.  
 
     
     
       5. The CAM cell of  claim 4 , wherein a drain region of the first transistor is coupled to a drain region of the second transistor at a first node. 
     
     
       6. The CAM cell of  claim 5 , further comprising a diode element coupled to the first node. 
     
     
       7. The CAM cell of  claim 6 , further comprising a local mask transistor coupled in series with the diode element. 
     
     
       8. The CAM cell of  claim 6 , wherein the diode element comprises a diode-connected transistor. 
     
     
       9. The CAM cell of  claim 6 , wherein the diode element comprises a P-N junction. 
     
     
       10. The CAM cell of  claim 6 , further comprising a match line coupled to the diode element, wherein the diode element is forward biased from the match line to the first node. 
     
     
       11. The CAM cell of  claim 10 , wherein the match line has a signal swing equal to a transistor threshold voltage. 
     
     
       12. The CAM cell of  claim 10 , further comprising a sensor circuit coupled to the match line, the sensor circuit pre-charging the match line to a voltage less than the V CC  supply voltage. 
     
     
       13. The CAM cell of  claim 12 , wherein the sensor circuit comprises a logic gate for providing an output signal that indicates whether a match or a no-match condition exists, the output signal having a signal swing equal to the V CC  supply voltage. 
     
     
       14. The CAM cell of  claim 1 , further comprising a bit line control circuit for biasing the second set of bit lines. 
     
     
       15. The CAM cell of  claim 14 , wherein the bit line control circuit comprises a first transistor for coupling the second set of bit lines during a pre-charge operation. 
     
     
       16. The CAM cell of  claim 14 , wherein the bit control circuit comprises one or more transistors for coupling the second set of bit lines to a voltage supply line during a global masking operation, the voltage supply line having a voltage less than the V CC  supply voltage. 
     
     
       17. The CAM cell of  claim 14 , wherein the bit line control circuit comprises a plurality of transistors for selectively coupling the second set of bit lines to a voltage supply line and a ground supply line, whereby the second set of bit lines receive voltages representative of the comparison data value from the voltage supply line and the ground supply line, the voltage supply line having a voltage less than the V CC  supply voltage. 
     
     
       18. The CAM cell of  claim 17 , wherein the voltage supply line has a voltage of two times a transistor threshold voltage. 
     
     
       19. The CAM cell of  claim 14 , wherein the bit line control circuit is powered by a supply voltage less than the V CC  supply voltage. 
     
     
       20. A content addressable memory (CAM) cell having a match line that carries a signal to indicate whether a match or a no-match condition exists within the CAM cell, wherein the difference between a voltage on the match line during the match condition and a voltage on the the match line during the no-match condition in equal to one transistor threshold voltage. 
     
     
       21. A method of operating a content addressable memory (CAM) cell that includes a static random access (SRAM) cell, the method comprising:
 operating the SRAM cell in response to a V CC  supply voltage, the SRAM cell storing a data value;  
 writing a data value to the SRAM cell on a first set of one or more bit lines, the first set of bit lines having a signal swing equal to the V CC  supply voltage;  
 reading data values from the SRAM cell on the first set of bit lines;  
 controlling the signal swing on the first set of bit lines to be equal to the V CC  supply voltage;  
 providing comparison data values to the CAM cell on a second set of bit lines; and  
 controlling the signal swing on the second set of bit lines to be less than the V CC  supply voltage.  
 
     
     
       22. The method of  claim 21 , further comprising the step of comparing the data value stored in the CAM cell with the comparison data value to determine whether a match condition or a no-match condition exists. 
     
     
       23. The method of  claim 22 , further comprising the step of indicating a match condition and a no-match audition by providing a signal having a signal swing equal to one transistor threshold voltage. 
     
     
       24. The method of  claim 22 , wherein the step of comparing comprises the step of coupling one of the bit lines in the second set of bit lines to a match line in response to the data value stored in the CAM cell. 
     
     
       25. The method of  claim 24 , further comprising the step of pre-charging the match line to a voltage less than the V CC  supply voltage. 
     
     
       26. The method of  claim 25 , further comprising the step of discharging the match line when a no-match condition exists. 
     
     
       27. The method of  claim 23 , further comprising the step of converting the signal having the signal swing of one transistor threshold voltage to a signal having a signal swing equal to the V CC  supply voltage. 
     
     
       28. The method of  claim 21 , further comprising the step of equalizing the second set of bit lines prior to providing the comparison data values to the CAM cell on the second set of bit lines. 
     
     
       29. The method of  claim 21 , further comprising the step of connecting the second set of bit lines to a voltages supply line during a global masking operation, the voltage supply line having a voltage less than the V CC  supply voltage. 
     
     
       30. The method of  claim 21 , further comprising the step of selectively coupling the second set of bit lines to a voltage supply line and a ground supply line, whereby the second set of bit lines receive voltages representative of the comparison data value from the voltage supply line and the ground supply line, the voltage supply line having a voltage less than the V CC  supply voltage. 
     
     
       31. The method of  claim 30 , wherein the voltage supply line has a voltage of two times a transistor threshold voltage. 
     
     
       32. The method of  claim 21 , further comprising the step of biasing the second set of bit lines with a supply voltage less than the V CC  supply voltage. 
     
     
       33. A method of operating a content addressable memory ( CAM )  array, comprising the steps of:      precharging first and second match sense lines that are electrically coupled to compare circuitry within a row of CAM cells to first and second positive voltage levels, respectively, said second voltage level having a maximum value that is less than Vcc, where Vcc is a power supply voltage supplied to the row of CAM cells;        applying a plurality of comparison data values to a plurality of comparison data lines that are electrically coupled to the row of CAM cells; and        detecting a match/no - match condition between the applied comparison data values and data stored in the row of CAM cells by sensing a voltage on the first match sense line in - sync with discharging the second match sense line from its precharged second positive voltage level.     
     
     
       34. The method of  claim 33 , wherein said detecting step comprises shorting the precharged first match sense line to the discharged second match sense line if a no- match condition is present between the applied comparison data values and the data stored in the row of CAM cells.   
     
     
       35. The method of  claim 33 , wherein the row of CAM cells is electrically coupled to a plurality of read/write bit lines; wherein said precharging step is preceded by the step of writing data into the row of CAM cells by driving at least some of the plurality of read/write bit lines at high logic levels that are about equal to Vcc; and wherein said applying step comprises driving at least some of the comparison data lines at high logic levels that are lower than Vcc by an amount equal to at least a transistor threshold voltage. 
     
     
       36. A content addressable memory ( CAM )  array, comprising the steps of:      a plurality of pairs of comparison data lines;        a row of CAM cells having compare circuitry therein that is electrically coupled to said plurality of pairs of comparison data lines;        first and second match sense lines that are electrically coupled to the compare circuitry in said row of CAM cells; and        a sensor circuit that is configured to disable the compare circuitry from indicating a match/no - match condition on the first match sense line by precharging the first and second match sense lines to first and second positive voltage levels, respectively, and is further configured to enable the compare circuitry to indicate a match/no - match condition on the first match sense line by discharging the second match sense line from its precharged second positive voltage level, said second positive voltage level having a maximum value that is less than Vcc by at least a transistor threshold voltage, where Vcc is a power supply voltage supplied to said row of CAM cells.     
     
     
       37. The CAM array of  claim 36 , wherein said sensor circuit is further configured to detect a voltage on the first match sense line as representing the match/no- match condition, in response to discharging the second match sense line from its precharged second positive voltage level.   
     
     
       38. The CAM array of  claim 37 , wherein an output of said sensor circuit is electrically coupled to an encoder. 
     
     
       39. The CAM array of  claim 37 , wherein said sensor circuit is responsive to at least one clock signal. 
     
     
       40. The CAM array of  claim 37 , wherein in response to being enabled by said sensor circuit, the compare circuitry is configured to short the first match sense line to the discharged second match sense line if a no- match condition is present between data applied to said plurality of pairs of comparison data lines and data entry stored in said row of CAM cells.   
     
     
       41. The CAM array of  claim 37 , wherein the compare circuitry comprises a plurality of local masking transistors having first current carrying terminals electrically connected to the second match sense line. 
     
     
       42. The CAM array of  claim 41 , wherein said row of CAM cells comprises SRAM- based memory cells therein; and wherein the local masking transistors are responsive to local mask enable signals.   
     
     
       43. The CAM array of  claim 42 , further comprising a plurality of pairs of read/write bit lines electrically coupled to the SRAM- based memory cells in said row of CAM cells.   
     
     
       44. The CAM array of  claim 37 , wherein the compare circuitry comprises a plurality of local masking transistors having first current carrying terminals electrically connected to the first match sense line. 
     
     
       45. The CAM array of  claim 44 , wherein said row of CAM cells comprises SRAM- based memory cells therein; and wherein the local masking transistors are responsive to local mask enable signals.   
     
     
       46. The CAM array of  claim 45 , further comprising a plurality of pairs of read/write bit lines electrically coupled to the SRAM- based memory cells in said row of CAM cells.   
     
     
       47. The CAM array of  claim 36 , wherein the compare circuitry comprises a plurality of XOR gates that are each associated with a respective CAM cell in said row of CAM cells. 
     
     
       48. A method of operating a content addressable memory ( CAM )  cell, comprising the steps of:      precharging first and second match sense lines that are electrically coupled to a compare circuit within the CAM cell to first and second positive voltage levels, respectively, said second positive voltage level having a maximum value that is less than Vcc, where Vcc is a power supply voltage supplied to the CAM cell;        applying a comparison data value to a pair of comparison data lines that are electrically coupled to the CAM cell; and        comparing the applied comparison data value with a data value stored in the CAM cell by discharging the second match sense line from its precharged second positive voltage level to a discharged voltage level and then sensing whether the first match sense line is maintained at its precharged first positive voltage level or is pulled down to the discharged voltage level by the compare circuit.     
     
     
       49. The method of  claim 48 , wherein said precharging step is performed in- sync with a first edge to a first clock signal; and wherein said comparing step is performed in - sync with a second edge of the first clock signal.   
     
     
       50. The method of  claim 48 , wherein the first and second positive voltage levels are equal. 
     
     
       51. The method of  claim 50 , wherein said applying step comprises driving at least one of the pair of comparison data lines with a signal having a voltage swing that is less than Vcc. 
     
     
       52. The method of  claim 48 , wherein said comparing step comprises shorting the first match sense line to the discharged second match sense line in the event a no- match condition exists between the applied comparison data value and the data value stored in the CAM cell.   
     
     
       53. The CAM array of  claim 36 , further comprising:
   a plurality of pairs of read/write bit lines that are electrically coupled to the CAM cells in said row of CAM cells; and        a bit line control circuit electrically coupled to said plurality of pairs of comparison data lines and said plurality of pairs of read/write bit lines, said bit line control circuit configured to support signal swings on said plurality of pairs of comparison data lines that are less than signal swings on said plurality of pairs of read/write bit lines.     
     
     
       54. The CAM array of  claim 53 , wherein the signal swings on said plurality of pairs of read/write bit lines are equal to about Vcc. 
     
     
       55. A CAM array, comprising:
   a CAM cell having a memory cell therein that is powered at a supply voltage;        a pair of read/write bit lines electrically coupled to said CAM cell;        a pair of comparison data lines electrically coupled to said CAM cell; and        a bit line control circuit electrically coupled to said pair of read/write bit lines and said pair of comparison bit lines, said bit line control circuit configured to support a signal swing on said pair of comparison bit lines that is less than a signal swing on said pair of read/write bit lines.     
     
     
       56. A CAM cell, comprising:
   a memory cell electrically coupled to a pair of read/write bit lines; and        a data comparison circuit electrically coupled to a pair of comparison bit lines, a match line and said memory cell, said data comparison circuit configured to indicate a mismatch between data stored in said memory cell and data applied to the pair of comparison bit lines during a comparison operation, by transferring charge between the match line and at least one of the pair of comparison bit lines.     
     
     
       57. The CAM cell of  claim 56 , wherein said data comparison circuit comprises a pair of N- channel transistors that are electrically connected in series between the pair of comparison bit lines.   
     
     
       58. The CAM cell of  claim 57 , wherein gate terminals of the pair of N- channel transistors are electrically coupled to said memory cell.   
     
     
       59. The CAM cell of  claim 58 , wherein the pair of N- channel transistors are joined together at a node; and wherein said data comparison circuit further comprises a first transistor having first current carrying terminal electrically coupled to the node.   
     
     
       60. The CAM cell of  claim 59 , wherein said data comparison circuit further comprises a local masking transistor having a first current carrying terminal electrically connected to the first transistor and a second current carrying terminal electrically connected to the match line. 
     
     
       61. A CAM array, comprising:
   a first CAM cell comprising a first memory cell electrically coupled to a first pair of read/write bit lines, and a first data comparison circuit electrically coupled to a first pair of comparison bit lines, a match line and said first memory cell, said first data comparison circuit configured to indicate a mismatch between data stored in said first memory cell and data applied to the first pair of comparison bit lines during a comparison operation, by transferring charge between the match line and at least one of the first pair of comparison bit lines; and        a second CAM cell comprising a second memory cell electrically coupled to a second pair of read/write bit lines, and a second data comparison circuit electrically coupled to a second pair of comparison bit lines, the match line and said second memory cell, said second data comparison circuit configured to indicate a mismatch between data stored in said second memory cell and data applied to the second pair of comparison bit lines during the comparison operation, by transferring charge between the match line and at least one of the second pair of comparison bit lines.     
     
     
       62. The CAM array of  claim 61 , wherein the first data comparison circuit comprises a first pair of N- channel transistors that are electrically connected in series between the first pair of comparison bit lines; and wherein the second data comparison circuit comprises a second pair of N - channel transistors that are electrically connected in series between the second pair of comparison bit lines.    
     
     
       63. The CAM array of  claim 62 , wherein gate terminals of the first pair of N- channel transistors are electrically coupled to the first memory cell.   
     
     
       64. The CAM array of  claim 62 , wherein the first pair of N- channel transistors are joined together at a first node; and wherein the first data comparison circuit further comprises a first transistor having a first current carrying terminal electrically coupled to the first node.   
     
     
       65. The CAM array of  claim 64 , wherein the second pair of N- channel transistors are joined together at a second node; and wherein the second data comparison circuit further comprises a second transistor having a first current carrying terminal electrically coupled to the second node.   
     
     
       66. The CAM array of  claim 65 , further comprising a sensor circuit having an output that is electrically coupled to gate terminals of the first and second transistors. 
     
     
       67. The CAM array of  claim 64 , wherein said first data comparison circuit further comprises a local masking transistor having a first current carrying terminal electrically connected to the first transistor and a second current carrying terminal electrically connected to the match line. 
     
     
       68. A CAM cell, comprising:
   a memory cell electrically coupled to a pair of read/write bit lines; and        a data comparison circuit electrically coupled to a pair of comparison bit lines, a match line and said memory cell, said data comparison circuit configured to indicate a mismatch between data stored in said memory cell and data applied to the pair of comparison bit lines during a comparison operation, by sinking current from the match line to at least one of the pair of comparison bit lines.