Large scale integrated circuit with sense amplifier circuits for low voltage operation

Abstract

Disclosed is a one-chip ULSI which can carry out the fixed operation in a wide range of power supply voltage (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which serves to a fixed internal voltage for a wide range of power supply voltage, an input/output buffer which can be adapted to several input/output levels, a dynamid RAM(s) which can operate at a power supply voltage of 2 V or less, etc. This one-chip ULSI can be applied to compact and portable electronic devices such as a lap-top type personal computer, an electronic pocket note book, a solid-state camera, etc.

1. A semiconductor device comprising:
 a plurality of data line pairs, a plurality of word lines intersecting said plurality of data line pairs, memory cells located at the intersecting points, sense amplifiers each for amplifying a difference voltage of a data line pair of said plurality of data line pairs to a first voltage in a term of an amplifying operation, and a common driving line pair for driving said sense amplifiers;    wherein the voltage amplitude between said common driving line pair is made larger than the maximum value of said first voltage between the data line pair in a part of the term of the amplifying operation.    
     
     
       2. A semiconductor device according to  claim 1 :
 wherein the common driving line pair is one of a plurality of common driving line pairs and, wherein the voltage of one of said common driving line pairs is boosted by boosting capacitors.    
     
     
       3. A semiconductor device according to  claim 1  further comprising:
 first, second and third power supply lines, and three switches connecting said first, second and third power supply lines with said common driving line pair respectively;    wherein the voltage between said first and second power supply lines is larger than the voltage between said second and third power supply lines which is substantially equal to the maximum value of said first voltage between the data line pair.    
     
     
       4. A semiconductor device according to  claim 3 ,
 wherein one of the voltages of the power supply lines is generated on the chip.    
     
     
       5. A semiconductor device comprising:
 a plurality of data lines, a plurality of word lines intersecting the plurality of data lines, memory cells located at the intersecting points, sense amplifiers each for amplifying a memory cell signal read out on each of the data lines, common driving lines for driving said sense amplifiers, and an internal voltage generator to generate a first internal voltage;    wherein said first internal voltage is substantially an intermediate value between a first external voltage and a second external voltage when the difference between the first and second external voltages is larger than a first reference voltage, whereas the difference between the first internal voltage and one of the external voltages is made constant when the difference between the first and the second external voltages is larger than a second reference voltage.    
     
     
       6. A semiconductor device comprising:
 a plurality of data lines, a plurality of word lines intersecting the plurality of data lines, memory cells located at the intersecting points, sense amplifiers each for amplifying a memory cell signal read out on each of the data lines, and common driving lines for driving said sense amplifiers;    wherein when said sense amplifiers start to operate, voltage of the data lines is varied to effectively boost an absolute value of the gate-source voltage of transistors in each of the sense amplifiers.    
     
     
       7. A semiconductor device according to  claim 6 , wherein said voltage of the data lines is boosted by capacitors. 
     
     
       8. A semiconductor device comprising:
 a plurality of data lines, a plurality of word lines intersecting the plurality of data lines, memory cells located at the intersecting points, sense amplifiers each for amplifying a memory cell signal read out on each of the data lines, and common driving lines for driving said sense amplifiers;    wherein said sense amplifiers operate with a voltage amplitude higher than that of the data lines and each of said sense amplifiers includes an inverter which operates with a voltage amplitude as that of the data lines.    
     
     
       9. A semiconductor device comprising:
 a plurality of data lines, a plurality of word lines intersecting the plurality of data lines, memory cells located at the intersecting points, sense amplifiers each for amplifying a memory cell signal read out on each of the data lines, and common driving lines for driving said sense amplifiers;    wherein a threshold voltage of each of the transistors in each of the sense amplifiers is varied in accordance with the operating condition of the sense amplifiers.    
     
     
       10. A semiconductor device according to  claim 9 , wherein said threshold voltage is varied dynamically. 
     
     
       11. A semiconductor device according to  claim 10 , wherein said threshold voltage is varied in range including 0 V. 
     
     
       12. A semiconductor device according to  claim 10 , wherein said threshold voltage is varied by varying a substrate voltage. 
     
     
       13. A semiconductor device comprising:
   circuit block including a first node and a second node for receiving an operating voltage and a plurality of complementary MISFETs, each having a p - channel MISFET and an n - channel MISFET connected in series between the first node and the second node,        wherein said semiconductor device has a first operation mode and a second operation mode,        wherein in the first operation mode, a first current between the first node and the second node flows through each of the plurality of complementary MISFETs when the voltage between the gate and the source of one of the p - channel MISFET and the n - channel MISFET is  0  volts for each of the plurality of complementary MISFETs,        wherein in the first operation mode, each of the p - channel and n - channel MISFETs have characteristics is that a leak current flows through the source - drain path even when the voltage between the gate and the source is  0  volts,        wherein in the second operation mode, a second current between the first node and the second node is smaller than the first current when the voltage between the gate and the source of one of the p - channel MISFET and the n - channel MISFET is  0  volts for each of the plurality of complementary MISFETs, and        wherein the operating voltage is between  0 . 5  V and  1 . 5  V.     
     
     
       14. A semiconductor device according to  claim 13 , further comprising a circuit for making the threshold voltage of the p- channel MISFETs be a first threshold voltage at the first operation mode or a second threshold voltage at the second operation mode and making the threshold voltage of the n - channel MISFETs be a third threshold voltage at the first operation mode or a fourth threshold voltage at the second operation mode.   
     
     
       15. A semiconductor device according to  claim 14 , wherein the first threshold voltage is larger than the second threshold voltage and the third threshold voltage is smaller than the fourth threshold voltage. 
     
     
       16. A semiconductor device according to  claim 15 , wherein the switching speed of the plurality of complementary MISFETs at the first operation mode is faster than that of the plurality of complementary MISFETs at the second operation mode. 
     
     
       17. A semiconductor device according to  claim 13 , wherein in the first operation mode, a leak current flowing through the source- drain path of each of the plurality of complementary MISFETs is about  1  μA when the voltage between the gate and the source of one of the p - channel MISFET and the n - channel MISFET is zero volt for each of the plurality of complementary MISFETs.   
     
     
       18. A semiconductor device according to  claim 13 ,
   wherein said semiconductor device is formed on a semiconductor substrate,        wherein the p - channel MISFETs of the plurality of complementary MISFETs are formed in a first semiconductor region with N - type,        wherein the N - channel MISFETs of the plurality of complementary MISFETs are formed in a second semiconductor region with P - type, and        wherein said semiconductor device further comprising a first voltage circuit for producing a first bias voltage supplied to the first semiconductor region and a second voltage circuit for producing a second bias voltage supplied to the second semiconductor region.     
     
     
       19. A semiconductor device according to  claim 18 ,
   wherein said semiconductor substrate has P - type,        wherein the second semiconductor region with P - type is isolated from the semiconductor substrate with P - type by a third semiconductor region with N - type, and        wherein the third semiconductor region is electrically connected to the first semiconductor region.     
     
     
       20. A semiconductor device according to  claim 19 ,
   wherein the first and second voltage circuit change the outputting voltage level depending on the first or second operation modes,        wherein the voltage of the first bias voltage at the first operation mode is lower than that of the first bias voltage at the second operation mode, and        wherein the voltage of the second bias voltage at the first operation mode is higher than that of the second bias voltage at the second operation mode.     
     
     
       21. A semiconductor device according to  claim 20 ,
   wherein the operating voltage is defined by a ground potential and a first potential higher than the ground potential, and        wherein the first bias voltage at the first operation is the first potential and the second bias voltage at the first operation mode is the ground potential.     
     
     
       22. A semiconductor device according to  claim 19 ,
   wherein the first voltage circuit includes a first oscillator and a first charge pumping circuit for generating the first bias voltage, and        wherein the second voltage circuit includes a second oscillator and a second charge pumping circuit for generating the second bias voltage.     
     
     
       23. A semiconductor device according to  claim 18 ,
   wherein the first operation mode is a high speed operation mode and the second operation mode is a low power consumption mode.     
     
     
       24. A semiconductor device according to  claim 18 , wherein said semiconductor device is an LSI chip including a microprocessor. 
     
     
       25. A semiconductor device comprising:
   a first circuit block including a first node, a second node, and a plurality of first complementary circuits, each having a P - channel first MISFET and an N - channel second MISFET connected in series between the first node and the second node,        a second circuit block including a third node, a fourth node, and a plurality of second complementary circuits, each having a P - channel third MISFET and an N - channel fourth MISFET connected in series between the third node and the fourth node,        wherein said semiconductor device has a first operation mode and a second operation mode,        wherein in the first operation mode, a first operating voltage is supplied between first and second nodes, a second operating voltage is supplied between third and fourth nodes, the threshold voltage of the P - channel third MISFETs is set to a first threshold voltage, and the threshold voltage of the N - channel fourth MISFETs is set to a second threshold voltage,        wherein in the second operation mode, no operating voltage is supplied between first and second nodes, the second operating voltage is supplied between third and fourth nodes,        the threshold voltage of the P - channel third MISFETs is set to a third threshold voltage, and the threshold voltage of the N - channel fourth MISFETs is set to a fourth threshold voltage, wherein the first threshold voltage is larger than the second threshold voltage and the third threshold voltage is smaller than the fourth threshold voltage.     
     
     
       26. A semiconductor device according to  claim 25 ,
   wherein said semiconductor device is a semiconductor LSI chip including a memory circuit, and        wherein the second circuit block includes a circuit for keeping information stored in the memory.     
     
     
       27. A semiconductor device according to  claim 25 , wherein the first operation mode is a high speed operation node and the second operation mode is a low power consumption mode. 
     
     
       28. A semiconductor device according to  claim 25 , wherein the operating voltage is between  0 . 5  V and  1 . 5  V. 
     
     
       29. A semiconductor device according to  claim 25 ,
   wherein in the first operation mode, each of the P - channel first MISFETs, the N - channel second MISFETs, the P - channel third MISFETs, and the N - channel fourth MISFETs have characteristics that a leak current flows through the source - drain path even when the voltage between the gate and the source is  0  volts.