Multi-bank testing apparatus for a synchronous dram

Abstract

A multi-bank testing apparatus for a synchronous DRAM, which allows all banks of the synchronous DRAM to simultaneously carry out their write and read operations in a test mode, thereby being capable of testing the entire bank in order to reduce the test time being likely to increase in accordance with an increased memory integration degree. The multi-bank testing apparatus includes a row address strobe generating unit for enabling a word line to transmit data from cells to bit line sense amplifiers in each bank of the synchronous DRAM, a column address strobe generating unit for generating a signal adapted to enable transistors respectively adapted to couple bit lines carrying data, amplified by the bit line sense amplifiers, to local data bus lines, input/output sense amplifiers for amplifying data on the local data bus lines, respectively, a transmission gate unit for controlling transmission of data from the input/output sense amplifiers to global read data bus lines, and an input/output comparing unit for compressing data from the input/output sense amplifiers prior to the transmission thereof to the global read data lines.

1. A multi-bank testing apparatus for a synchronous DRAM consisting of a plurality of banks, comprising:
 a row address strobe generating unit for generating a signal adapted to simultaneously enable all of word lines having a same row address of each bank to transit data from cells to bit line sense amplifiers in each bank of said synchronous DRAM;  
 a column address strobe generating unit for generating a signal adapted to enable transistors respectively adapted to simultaneously couple bit lines having a same column address of each bank and carrying data, amplified by said bit line sense amplifiers, to local data bus lines;  
 input/output sense amplifiers for amplifying data on said local data bus lines, respectively;  
 a transmission gate unit for controlling transmission of data from said input/output sense amplifiers to global read data bus lines; and  
 an input/output comparing unit for compressing data from said input/output sense amplifiers prior to said transmission thereof to said global read data bus lines.  
 
     
     
       2. The multi-bank testing apparatus as claimed in  claim 1 , wherein said row address strobe generating unit comprises:
 a first PMOS transistor and a first NMOS transistor connected in series to each other, said first PMOS and NMOS transistors receiving a row address strobe signal in a common fashion at gates thereof;  
 a timing controller coupled to a node between said first PMOS and NMOS transistors and adapted to control the period of time for which an output from said row address strobe generating unit;  
 a group of second NMOS transistors coupled in series together and connected in series to said first NMOS transistor, each of said second NMOS transistors receiving an associated one of bank selection address signals at a gate thereof;  
 a third NMOS transistor coupled to a node between said first NMOS transistor and said second NMOS transistor group in a fashion parallel to said second NMOS transistor group, said third NMOS transistor receiving, at a gate thereof, an all-bank test signal being enabled when write and read operations in a test mode are to be conducted for all banks.  
 
     
     
       3. The multi-bank testing apparatus as claimed in  claim 1 , wherein said column address strobe generating unit comprises:
 a first PMOS transistor and a first NMOS transistor connected in series to each other, said first PMOS and NMOS transistors receiving a column address strobe signal in a common fashion at gates thereof;  
 a timing controller coupled to a node between said first PMOS and NMOS transistors and adapted to control the period of time for which an output from said column address strobe generating unit;  
 a group of second NMOS transistors coupled in series together and connected in series to said first NMOS transistor, each of said second NMOS transistors receiving an associated one of bank selection address signals at a gate thereof;  
 a third NMOS transistor coupled to a node between said first NMOS transistor and said second NMOS transistor group in a fashion parallel to said second NMOS transistor group, said third NMOS transistor receiving, at a gate thereof, an all-bank test signal being enabled when write and read operations in a test mode are to be conducted for all banks.  
 
     
     
       4. The multi-bank testing apparatus as claimed in  claim 1 , wherein said transmission gate unit comprises:
 a plurality of first transmission gates each arranged between an output of an associated one of said input/output sense amplifiers and an associated one of said global read data bus lines, each of said first transmission gates being closed in response to an all-bank test signal being enabled when write and read operations in a test mode are to be conducted for all banks, thereby preventing data from said associated input/output sense amplifier from being transmitted to said associated global read data bus line; and  
 a pair of second transmission gates each arranged between an output of said input/output comparing unit and an associated one of said input/output global read data bus lines, each of said second transmission gates being opened by said all-bank test signal, thereby allowing said output from said input/output comparing unit to be transmitted to said associated global read data bus line.  
 
     
     
       5. The multi-bank testing apparatus as claimed in  claim 4 , wherein:
 each of said first transmission gate comprises 
 a first PMOS transistor and a first NMOS transistor coupled in parallel between said associated input/output sense amplifier and a first one of two global read data bus lines respectively associated with input and input-bar signals from said input/output sense amplifier, said first PMOS transistor receiving, at a gate thereof, said all-bank test signal while said first PMOS transistor receiving, at a gate thereof, a signal inverted from said all-bank test signal via an inverter, and  
 a second PMOS transistor and a second NMOS transistor coupled in parallel between said associated input/output sense amplifier and a second one of said associated global read data bus lines, said second PMOS transistor receiving, at a gate thereof, said all-bank test signal while said second NMOS transistor receiving, at a gate thereof, a signal inverted from said all-bank test signal via said inverter; and each of said second transmission gates comprises  
 a third PMOS transistor and a third NMOS transistor coupled in parallel between said input/output comparing unit and said first associated global read data bus line, said third PMOS transistor receiving, at a gate thereof, said signal inverted from said all-bank test signal via said inverter while said third NMOS transistor receiving, at a gate thereof, said all-bank test signal, and  
 a fourth PMOS transistor and a fourth NMOS transistor coupled in parallel between said input/output comparing unit and said second associated global read data bus line, said fourth PMOS transistor receiving, at a gate thereof, said signal inverted from said all-bank test signal via said inverter whereas said fourth NMOS transistor receiving, at a gate thereof, said all-bank test signal.  
 
 
     
     
       6. The multi-bank testing apparatus as claimed in  claim 1 , wherein said input/output comparing unit comprises:
 a pair of first PMOS transistors and a pair of first NMOS transistors coupled together in parallel and adapted to receive, at respective gates thereof, a signal inverted by an inverter from an all-bank test signal being enabled when write and read operations in a test mode are to be conducted for all banks;  
 a plurality of second PMOS transistors coupled in parallel between one of said first PMOS transistors and one of said first NMOS transistors and adapted to receive, at respective gates thereof, input signals;  
 a second NMOS transistor coupled to one of said first NMOS transistors in such a fashion that they have a common source;  
 a plurality of third PMOS transistors coupled in parallel between the other one of said first PMOS transistors and the other one of said first NMOS transistors and adapted to receive, at respective gates thereof, input-bar signals;  
 a third NMOS transistor connected to other one of said first NMOS transistors in such a fashion that they have a common source;  
 a first NAND gate adapted to receive said input and input-bar signals;  
 a second NAND gate adapted to receive an output from said first NAND gate at one input thereof, said second NAND gate also receiving said all-bank test signal at the other input thereof; and  
 a third NAND gate adapted to receive an output from said second NAND gate via inverters at one input thereof, said third NAND gate also receiving an output from said second NAND gate via said inverters and then via other inverters, said third NAND gate being coupled at an output thereof to gates of said second and third NMOS transistors in a common fashion via an inverter.  
 
     
     
       7. The multi-bank testing apparatus as claimed in  claim 6 , wherein said input and input-bar signals are those output from said input/output sense amplifiers transmitted to the same global read data bus line and enabled in response to the same column address. 
     
     
       8. The multi-bank testing apparatus as claimed in  claim 6 , wherein said input and input-bar signals are those output from said input/output sense amplifiers associated with the same bank and enabled in response to the same column address. 
     
     
       9. A multi- bank testing apparatus for a memory circuit having a plurality of banks, the apparatus comprising:      a row address strobe generator configured to generate a signal adapted to simultaneously enable word lines having a same row address in more than one of said plurality of banks to transmit information from cells to respective bit line sense amplifiers;        a column select circuit configured to couple bit lines from said bit line sense amplifiers to respective local data bus lines;        a column address strobe generator configured to generate a signal adapted to enable the column select circuit to simultaneously couple respective bit lines having a same column address in more than one of said plurality of banks to respective local data bus lines;        a plurality of input/output sense amplifiers each configured to amplify data from a respective one of said data bus lines;        a transmission gate unit for controlling transmission of data from said input/output sense amplifiers to global read data bus lines; and        an input/output comparing unit for compressing data from said input/output sense amplifiers prior to said transmission thereof to said global read data bus lines.     
     
     
       10. A synchronous dynamic random access memory ( SDRAM ) , comprising:      a plurality of banks, each bank having:      a plurality of memory cells for storing data, the memory cells arranged in rows and columns;        a plurality of bit lines, each bit line configured to carry signals from one of the columns of memory cells;        a plurality of word lines, each word line configured to couple memory cells of one of the rows to respective ones of the bit lines;        a plurality of bit line sense amplifiers, each coupled to a respective one of the bit lines;        a local data bus line;        a column select circuit configured to couple an output of a selected one of the bit line sense amplifiers to the local data bus line; and        an input/output amplifier coupled to receive signals from the local data bus line;          a row address strobe  ( RAS )  enable generating circuit configured to generate a plurality of RAS enable signals, the RAS enable signals being adapted to simultaneously enable one of the word lines of each of the plurality of banks during a test operation;        a column address strobe  ( CAS )  enable generating circuit configured to generate a plurality of CAS enable signals, the CAS enable signals being adapted to simultaneously enable the column select circuit of each of the plurality of banks during the test operation;        a global read data bus line;        an input/output comparing unit configured to compare data from the input/output sense amplifiers of the plurality of banks during the test operation; and        a transmission gate block configured to control transmission of data from the input/output amplifier of each bank and the input/output comparing unit to the global read data bus line.     
     
     
       11. The SDRAM of  claim 10 , wherein during the test operation, the input/output comparing unit compares the data from the input/output sense amplifier of a first one of the plurality of banks to the data from the input/output sense amplifier of a second one of the plurality of banks. 
     
     
       12. The SDRAM of  claim 10 , wherein the input/output comparing unit comprises a multi- bit test circuit.   
     
     
       13. The SDRAM of  claim 12 , wherein the multi- bit test circuit is configured to compare respective logic states of a plurality of bits of data received from the input/output sense amplifiers to a known pattern of logic states.   
     
     
       14. The SDRAM of  claim 13 , wherein the known pattern of logic states comprises a plurality of bits each having the same logic state. 
     
     
       15. The SDRAM of  claim 10 , wherein the RAS enable signals are further adapted to enable one of the word lines in one of the plurality of banks during a normal operation, and wherein the CAS enable signals are further adapted to enable the column select circuit of one of the plurality of banks during a normal operation. 
     
     
       16. The SDRAM of  claim 15 , wherein the transmission gate block is further configured to transmit signals from the input/output comparing unit to the global read data bus line during the test operation and to transmit signals from the input/output amplifier of an enabled one of the plurality of banks to the global read data bus line during a normal operation. 
     
     
       17. The SDRAM of  claim 10 , wherein during the test operation, data is simultaneously transmitted from a selected memory cell of each bank to the input/output comparing unit, wherein the selected memory cells have corresponding row addresses and column addresses. 
     
     
       18. The SDRAM of  claim 17 , wherein the selected memory cell of each bank is a memory cell to which data was previously written during a write test cycle of the test operation. 
     
     
       19. The SDRAM of  claim 10 , wherein the RAS enable generating circuit is further configured to receive a test mode signal and a bank selection signal and to override the bank selection signal when the test mode signal is in an asserted state. 
     
     
       20. The SDRAM of  claim 10 , wherein the RAS enable generating circuit includes:
   a first transistor coupled between a power supply potential and a first node, the first transistor having a gate terminal coupled to receive a row address strobe signal;        a second transistor coupled between the first node and a second node, the second transistor having a gate terminal coupled to receive the row address strobe signal;        a plurality of bank selection transistors serially coupled between the second node and a ground potential, each of the bank selection transistors having a gate terminal coupled to receive a respective bank selection address signal;        a test mode transistor coupled between the second node and the ground potential, the test mode transistor having a gate terminal coupled to receive a test mode signal; and        a timing control circuit coupled between the first node and an output node and configured to control a duration of an asserted state of a RAS enable signal on the output node.     
     
     
       21. The SDRAM of  claim 10 , wherein the CAS enable generating circuit includes:
   a first transistor coupled between a power supply potential and a first node, the first transistor having a gate terminal coupled to receive a column address strobe signal;        a second transistor coupled between the first node and a second node, the second transistor having a gate terminal coupled to receive the column address strobe signal;        a plurality of bank selection transistors serially coupled between the second node and a ground potential, each of the bank selection transistors having a gate terminal coupled to receive a respective bank selection address signal;        a test mode transistor coupled between the second node and the ground potential, the test mode transistor having a gate terminal coupled to receive a test mode signal; and        a timing control circuit coupled between the first node and an output node and configured to control a duration of an asserted state of a CAS enable signal on the output node.     
     
     
       22. A method for testing a memory device having a plurality of banks of memory cells, the method comprising:
   performing a write operation, including the acts of:      simultaneously enabling more than one of the plurality of banks; and        simultaneously writing write - test data to a selected memory cell in each of the plurality of enabled banks, the selected memory cell in each of the plurality of enabled banks having corresponding row addresses and column addresses;          performing a read operation, including the acts of:      simultaneously enabling more than one of the plurality of banks, including generating a RAS enable signal in an asserted state for each of the plurality of enabled banks, thereby simultaneously enabling a word line of each of the plurality of enabled banks, the enabled word line of each of the plurality of enabled banks corresponding to the same row address; and        simultaneously reading read - test data from the selected memory cell in each of the plurality of enabled banks;          comparing the read - test data from each of the plurality of enabled banks; and        generating a result signal based on a result of the act of comparing.     
     
     
       23. The method of  claim 22 , further comprising:
   transmitting the result signal on a global read data bus line of the memory device.     
     
     
       24. The method of  claim 22 , wherein the write- test data includes data having a same logic state.   
     
     
       25. The method of  claim 24 , wherein the result signal indicates whether the read- test data correspond to the same logic state.   
     
     
       26. The method of  claim 22 , wherein the act of reading includes:
   generating a CAS enable signal in an asserted state for each of the plurality of enabled banks, thereby simultaneously enabling a column select circuit of each of the plurality of enabled banks to select a column, the selected column of each of the plurality of enabled banks corresponding to the same column address.     
     
     
       27. A method for testing a memory device having a plurality of banks of memory cells, the method comprising:
   performing a write operation, including the acts of:      simultaneously enabling more than one of the plurality of banks; and        simultaneously writing write - test data to a selected memory cell in each of the plurality of enabled banks, the selected memory cell in each of the plurality of enabled banks having corresponding row addresses and column addresses;          performing a read operation, including the acts of:      simultaneously enabling more than one of the plurality of banks, including generating a CAS enable signal in an asserted state for each of the plurality of enabled banks, thereby simultaneously enabling a column select circuit of each of the plurality of enabled banks to select a column, the selected column of each of the plurality of enabled banks corresponding to the same column address; and        simultaneously reading read - test data from the selected memory cell in each of the plurality of enabled banks;          comparing the read - test data from each of the plurality of enabled banks; and        generating a result signal based on a result of the act of comparing.