Silicon-on-insulator chip having an isolation barrier for reliability

Abstract

An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.

1. A silicon-on-insulator (SOI) semiconductor chip comprising:
 a peripheral edge;  
 a substrate;  
 an oxide layer on the substrate;  
 a silicon layer on the oxide layer;  
 an active area;  
 an isolation barrier including a groove: 
 (a) being disposed slightly inward of the peripheral edge of the chip,  
 (b) extending through the silicon layer and through the oxide layer and partially into the substrate to prohibit impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier, and  
 (c) surrounding completely the active area of the chip, and  
 
 a passivation layer on the silicon layer and extending to the groove, and  
   a barrier material located over the passivation layer.    
 
     
     
       2. The SOI chip according to  claim 1  wherein the active area of the chip includes a gate located on the silicon layer, a gate metal contact deposited above and forming an electrical contact with the gate, and at least one metal contact deposited above and forming an electrical contact with the silicon layer. 
     
     
       3. The SOI chip according to  claim 1  wherein the passivation layer is selected from the group consisting of silicon nitride, polysilicon, oxide, and nitride. 
     
     
       4. The SOI chip according to  claim 1  further comprising a  wherein the barrier material located (i) over the passivation layer on the silicon layer, and (ii) in  extends into the groove presenting an additional barrier to impurities in the oxide layer outside the groove from diffusing into the oxide layer inside the groove. 
     
     
       5. The SOI chip according to  claim 4  wherein the barrier material is dielectric. 
     
     
       6. The SOI chip according to  claim 5  wherein the barrier material is selected from the group consisting of phosphosilicate glass (PSG), BPSG, nitride and oxide. 
     
     
       7. The SOI chip according to  claim 1  further comprising the passivation layer on the silicon layer and in the groove. 
     
     
       8. The SOI chip according to  claim 7  wherein the passivation layer is selected from the group of silicon nitride, polysilicon, oxide, and nitride. 
     
     
       9. The SOI chip according to  claim 7  further comprising an oxide located in the groove and over the passivation layer which is on the silicon layer and in the groove. 
     
     
       10. The SOI chip according to  claim 7  further comprising a barrier material located on the passivation layer, over the silicon layer and in the groove, presenting an additional barrier to impurities in the oxide layer outside the groove from diffusing into the oxide layer inside the groove. 
     
     
       11. The SOI chip according to  claim 10  wherein the barrier material is dielectric. 
     
     
       12. The SOI chip according to  claim 11  wherein the barrier material is selected from the group consisting of phosphosilicate glass (PSG), BPSG, and nitride. 
     
     
       13. The SOI chip according to  claim 10  further comprising an oxide located in the groove and over the barrier material and the passivation layer which are in the groove. 
     
     
       14. The SOI chip according to  claim 1  wherein the groove is defined by side walls and an open bottom, the SOI chip further comprising the passivation layer on the silicon layer and the side walls of the groove with the bottom of the groove devoid of the passivation layer. 
     
     
       15. The SOI chip according to  claim 14  wherein the passivation layer is selected from the group consisting of silicon nitride, polysilicon, oxide, and nitride. 
     
     
       16. The SOI chip according to  claim 14  further comprising a fill material deposited in the groove adjacent the passivation layer on the side walls of the groove and contacting the substrate through the open bottom of the groove. 
     
     
       17. The chip according to  claim 16  wherein the fill material is polysilicon. 
     
     
       18. The SOI chip according to  claim 17  wherein the polysilicon fill material is doped conductive, forming an electrical contact with the substrate. 
     
     
       19. The SOI chip according to  claim 18  further comprising a metal contact extending from the doped conductive fill material and forming an electrical contact with substrate. 
     
     
       20. The SOI chip according to  claim 1  wherein the groove has a width of about 1-2 microns. 
     
     
       21. A silicon-on-insulator (SOI) semiconductor chip comprising:
 a peripheral edge;  
 a substrate;  
 an oxide layer on the substrate;  
 a silicon layer on the oxide layer;  
 a passivation layer on the silicon layer;  
 an active area including a gate located above the silicon layer, a gate metal contact located above and forming an electrical contact with the gate, and at least one metal contact located above and forming an electrical contact with the silicon layer;  
 an isolation barrier, including a groove: 
 (a) being disposed slightly inward of the peripheral edge of the chip,  
 (b) extending through the silicon layer and through the oxide layer and partially into the substrate to prohibit impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier, and  
 (c) surrounding completely the active area of the chip;  
 
 a barrier material located (I) over the passivation layer on the silicon layer, and (ii) in the groove, presenting an additional barrier to impurities in the oxide layer outside the groove from diffusing into the oxide layer inside the groove.  
 
     
     
       22. A silicon-on-insulator (SOI) semiconductor chip comprising:
 a peripheral edge;  
 a substrate;  
 an oxide layer on the substrate;  
 a silicon layer on the oxide layer;  
 a passivation layer on the silicon layer;  
 an active area;  
 an isolation barrier, including a groove: 
 (a) being disposed slightly inward of the peripheral edge of the chip,  
 (b) extending through the silicon layer and through the oxide layer and partially into the substrate to prohibit impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier, and  
 (c) surrounding completely the active area of the chip;  
 
 a barrier material located: 
 (a) over the passivation layer on the silicon layer, and  
 (b) in the groove, presenting an additional barrier to impurities in the oxide layer outside the groove from diffusing into the oxide layer inside the groove.  
 
 
     
     
       23. The SOI chip according to  claim 22  wherein the passivation layer is selected from the group consisting of silicon nitride, polysilicon, oxide, and nitride. 
     
     
       24. The SOI chip according to  claim 22  wherein the barrier material is dielectric. 
     
     
       25. The SOI chip according to  claim 24  wherein the barrier material is selected from the group consisting of phosphosilicate glass (PSG), BPSG, nitride and oxide that prevents impurities in said oxide layer outside said isolation barrier from diffusing into said oxide layer inside said isolation barrier. 
     
     
       26. The SOI chip according to  claim 22  wherein the groove has a width of about 1-2 microns. 
     
     
       27. The SOI chip according to  claim 22  wherein the groove in the isolation barrier extends through the passivation layer. 
     
     
       28. A silicon-on-insulator (SOI) semiconductor chip comprising:
 a peripheral edge;  
 a substrate;  
 an oxide layer on the substrate;  
 a silicon layer on the oxide layer;  
 an active area;  
 an isolation barrier: 
 (a) including a groove defined by side walls and an open bottom,  
 (b) being disposed slightly inward of the peripheral edge of the chip,  
 (c) extending through the silicon layer and through the oxide layer and partially into the substrate to prohibit impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier, and  
 (d) surrounding completely the active area of the chip;  
 
 a passivation layer on the silicon layer and the side walls of the groove with the bottom of the groove devoid of the passivation layer;  
 a doped conductive fill material located in the groove adjacent the passivation layer on the sidewalls of the groove forming an electrical contact with the substrate and contacting the substrate through the open bottom of the groove; and  
 a metal contact extending from the doped conductive fill material and forming an electrical contact with the doped conductive fill material.  
 
     
     
       29. The SOI chip according to  claim 28  wherein the passivation layer is selected from the group consisting of silicon nitride, polysilicon, oxide, and nitride. 
     
     
       30. The SOI chip according to  claim 28  wherein the fill material is polysilicon. 
     
     
       31. The SOI chip according to  claim 29  wherein the barrier material is polysilicon. 
     
     
       32. The SOI chip according to  claim 31  wherein the barrier material is dielectric. 
     
     
       33. The SOI chip according to  claim 32  wherein the barrier material is selected from the group consisting of phosphosilicate glass (PSG), BPSG, nitride and oxide that prevents impurities in said oxide layer outside said isolation barrier from diffusing into said oxide layer inside said isolation barrier. 
     
     
       34. The SOI chip according to  claim 31  further comprising an oxide located in the groove and over the barrier material and the passivation layer which are in the groove. 
     
     
       35. The SOI chip according to  claim 22  wherein the barrier material is conductive. 
     
     
       36. A silicon-on-insulator (SOI) semiconductor chip comprising:
 a peripheral edge;  
 a substrate;  
 an oxide layer on the substrate;  
 a silicon layer on the oxide layer;  
 an active area;  
 an isolation barrier, including a groove: 
 (a) being disposed slightly inward of the peripheral edge of the chip,  
 (b) extending through the silicon layer and through the oxide layer and partially into the substrate to prohibit impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier, and  
 (c) surrounding completely the active area of the chip;  
 
 a passivation layer on the silicon layer and in the groove; and  
 a barrier material located in the passivation layer, over the silicon layer, and in the groove presenting an additional barrier to impurities in the oxide layer outside the groove from diffusing into the oxide layer inside the groove.  
 
     
     
       37. A silicon-on-insulator (SOI) semiconductor chip comprising:
 a peripheral edge;    a substrate;    an oxide layer on the substrate;    a silicon layer on the oxide layer;    an active area;    an isolation barrier, including a groove: 
 (a) being disposed slightly inward of the peripheral edge of the chip,  
 (b) extending through the silicon layer and through the oxide layer and partially into the substrate to prohibit impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier, and  
 (c) surrounding completely the active area of the chip.  
   
     
     
       38. A silicon-on-insulator (SOI) semiconductor chip comprising:
 a peripheral edge;    a substrate;    an oxide layer on the substrate;    a silicon layer on the oxide layer;    an active area;    an isolation barrier, including a groove: 
 (a) being disposed slightly inward of the peripheral edge of the chip,  
 (b) extending through the silicon layer and through the oxide layer and partially into the substrate to prohibit impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier, and  
 (c) surrounding completely the active area of the chip; and  
   a passivation layer on the silicon layer and extending to and partially over the groove.    
     
     
       39. A semiconductor chip comprising:
   a peripheral edge;        a substrate;        a semiconductor device formed on the substrate;        an isolation barrier including a groove;    ( a )  being disposed slightly inward of the peripheral edge of the chip and surrounding the semiconductor device, and      ( b )  prohibiting impurities outside the isolation barrier from diffusing into the semiconductor device inside the isolation barrier,          a passivation layer over at least a portion of the semiconductor device and extending to the groove; and        wherein the substrate is a semiconductor and the semiconductor device includes a gate and a silicide layer, a gate metal contact deposited above and forming an electrical contact with the gate, and at least one metal contact deposited above and forming an electrical contact with the substrate.     
     
     
       40. The chip of  claim 39 , wherein the isolation barrier further comprises a fill material located within the groove, making a direct contact to the substrate. 
     
     
       41. The chip of  claim 40 , wherein the fill material is polysilicon. 
     
     
       42. The chip of  claim 39 , wherein the semiconductor device comprises one or more layers formed on the substrate and wherein the groove extends through the one or more layers to at least the substrate. 
     
     
       43. The chip of  claim 42 , wherein the passivation layer is formed over the one or more layers. 
     
     
       44. The chip according to  claim 39 , wherein the passivation layer is selected from the group consisting of silicon nitride, polysilicon, doped and undoped silicon oxide, and silicon nitride. 
     
     
       45. The chip according to  claim 39 , further comprising a barrier material located in the groove presenting an additional barrier to impurities outside the isolation barrier from diffusing into the semiconductor device inside the isolation barrier. 
     
     
       46. The chip according to  claim 45 , wherein the barrier material is a dielectric. 
     
     
       47. The chip according to  claim 46 , wherein the barrier material is selected from a group consisting of phosphosilicate glass ( PSG ) , BPSG, silicon nitride and silicon oxide.   
     
     
       48. The chip according to  claim 39 , wherein the passivation layer extends into the groove. 
     
     
       49. The chip according to  claim 48 , wherein the passivation layer is selected from a group consisting of silicon nitride, polysilicon, oxide, and nitride. 
     
     
       50. The chip according to  claim 48 , further comprising an oxide located in the groove and over the passivation layer in the groove. 
     
     
       51. The chip according to  claim 48 , further comprising a barrier material located on the passivation layer and in the groove presenting an additional barrier to impurities outside the isolation barrier from diffusing into the semiconductor device inside the isolation barrier. 
     
     
       52. The chip according to  claim 51 , wherein the barrier material is a dielectric. 
     
     
       53. The chip according to  claim 52 , wherein the barrier material is selected from a group consisting of phosphosilicate glass ( PSG ) , BPSG, and nitride.   
     
     
       54. The chip according to  claim 51 , further comprising an oxide located in the groove and over the barrier material and the passivation layer which are in the groove. 
     
     
       55. The chip according to  claim 39 , wherein the groove is defined by side walls and an open bottom, the chip further comprising the passivation layer on the side walls of the groove with the bottom of the groove devoid of the passivation layer. 
     
     
       56. The chip according to  claim 55 , wherein the passivation layer is selected from a group consisting of silicon nitride, polysilicon, oxide, and nitride. 
     
     
       57. The chip according to  claim 55 , further comprising a fill material deposited in the groove adjacent the passivation layer on the side walls of the groove and contacting the substrate through the open bottom of the groove. 
     
     
       58. The chip according to  claim 57 , wherein the fill material is polysilicon. 
     
     
       59. The chip according to  claim 57 , wherein the fill material is a conductor forming an electrical contact with the substrate. 
     
     
       60. The chip according to  claim 59 , further comprising a metal contact extending from the conductive fill material and forming an electrical contact with the substrate. 
     
     
       61. The chip according to  claim 39 , wherein the groove has a width of about  1 -   2  microns.   
     
     
       62. A semiconductor chip comprising:
   a peripheral edge;        a substrate;        a semiconductor device formed on the substrate, the semiconductor device including a gate and a silicide layer, a gate metal contact located above and forming an electrical contact with the gate, and at least one metal contact located above and forming an electrical contact with the substrate;        a passivation layer over at least a portion of the semiconductor device on the silicon layer;        an isolation barrier, including a groove:    ( a )  being disposed slightly inward of the peripheral edge of the chip and surrounding the semiconductor device, and      ( b )  prohibiting impurities outside the isolation barrier from the diffusing into the semiconductor device inside the isolation barrier,          a barrier material located    ( i )  over the passivation layer and      ( ii )  in the groove, presenting an additional barrier to impurities outside the isolation barrier from diffusing into the semiconductor device inside the isolation barrier.       
     
     
       63. A semiconductor chip comprising:
   a peripheral edge;        a substrate;        a semiconductor device formed on the substrate;        a passivation layer over at least a portion of the semiconductor;        an isolation barrier, including a groove:    ( a )  being disposed slightly inward of the peripheral edge of the chip and surrounding the semiconductor device, and      ( b )  prohibiting impurities outside the isolation barrier from diffusing into the semiconductor device inside the isolation barrier,          a barrier material located:    ( a )  over the passivation layer, and      ( b )  in the groove, presenting an additional barrier to impurities outside the isolation barrier from diffusing into the semiconductor device inside the isolation barrier.       
     
     
       64. The chip according to  claim 63 , wherein the passivation layer is selected from a group consisting of silicon nitride, polysilicon, doped and undoped silicon oxide, and silicon nitride. 
     
     
       65. The chip according to  claim 63 , wherein the barrier material is a dielectric. 
     
     
       66. The chip according to  claim 65 , wherein the barrier material is selected from a group consisting of phosphosilicate glass ( PSG ) , BPSG, silicon nitride and silicon oxide that prevents impurities outside said isolation barrier from diffusing into said semiconductor device inside said isolation barrier.   
     
     
       67. The chip according to  claim 63 , wherein the groove has a width of about  1 -   2  microns.   
     
     
       68. The chip according to  claim 63 , wherein the groove in the isolation barrier extends through the passivation layer. 
     
     
       69. A semiconductor chip comprising:
   a peripheral edge;        a substrate;        a semiconductor device formed on the substrate;        an isolation barrier:    ( a )  including a groove defined by side walls and an open bottom,      ( b )  being disposed slightly inward of the peripheral edge of the chip and surrounding the semiconductor device, and      ( c )  prohibiting impurities outside the isolation barrier from diffusing into the semiconductor device inside the isolation barrier,          a passivation layer over at least a portion of the semiconductor device and the side walls of the groove with the bottom of the groove devoid of the passivation layer;        a conductive fill material located in the groove adjacent the passivation layer on the sidewalls of the groove forming an electrical contact with the substrate and contacting the substrate through the open bottom of the groove; and        a metal contact extending from the conductive fill material and forming an electrical contact with the conductive fill material.     
     
     
       70. The chip according to  claim 69 , wherein the passivation layer is selected from a group consisting of silicon nitride, polysilicon, doped and undoped silicon oxide, and silicon nitride. 
     
     
       71. The chip according to  claim 70 , wherein the barrier material is polysilicon. 
     
     
       72. The chip according to  claim 71 , wherein the barrier material is a dielectric. 
     
     
       73. The chip according to  claim 72 , wherein the barrier material is selected from a group consisting of phosphosilicate glass ( PSG ) , BPSG, silicon nitride and silicon oxide that prevents impurities said isolation barrier from diffusing into said semiconductor device inside said isolation barrier.   
     
     
       74. The chip according to  claim 73 , wherein the barrier material is conductive. 
     
     
       75. The chip according to  claim 71 , further comprising an oxide located in the groove and over the barrier material and the passivation layer which are in the groove.