Sample and load scheme for observability internal nodes in a PLD

Abstract

A programmable logic device (PLD) that provides the capability to observe and control the logic state of buried internal nodes is disclosed. The PLD provides shadow storage units for internal nodes such as logic element registers, memory cells, and I/O registers. A sample/load data path includes bidirectional data buses and shift register that facilitate the sampling of internal nodes for observing their logic states, and loading of internal nodes for controlling their logic states.

1. In a programmable logic device (PLD), an input/output (I/O) architecture comprising:
 a plurality of I/O cells disposed along a periphery of the PLD and coupled to respective I/O terminals, each I/O cell having an I/O register; and  
 a plurality of shadow I/O storage units corresponding, and respectively coupled, to said plurality of I/O registers,  
 wherein, in an observable mode, data is selectively sampled from an I/O register in an I/O cell into a respective shadow I/O storage unit, and made available on an I/O terminal.  
 
     
     
       2. The I/O architecture of  claim 1  wherein said plurality of shadow I/O storage units form a serial chain between a PLD input terminal and a PLD output terminal when coupled together via a corresponding plurality of pass transistors, a control terminal of said plurality of pass transistors being coupled to a logic OR combination of a pre-load and observe control signals. 
     
     
       3. The I/O architecture of  claim 2  wherein said plurality of shadow I/O storage units are a plurality of registers used for JTAG boundary scan testing. 
     
     
       4. A programmable logic device (PLD) with observable and controllable internal nodes, said PLD comprising:
 a plurality of logic elements coupled by an interconnect network, each logic element comprising a primary register coupled to a shadow storage unit;  
 a memory array having a plurality of primary memory cells respectively coupled to a corresponding plurality of shadow storage units; and  
 a plurality of input/output (I/O) cells respectively coupled to a corresponding plurality of I/O terminals, each I/O cell comprising a primary I/O register coupled to a shadow storage unit,  
 wherein, in an observe mode of operation, data is selectively sampled from said primary register, primary memory cell and primary I/O register into their respective shadow storage units and made available on PLD I/O terminal, and  
 wherein, in a load mode of operation, data is selectively loaded from shadow storage units into respective primary register, memory cell and I/O register.  
 
     
     
       5. A method for observing and controlling the logic state of internal nodes of a probable  programmable logic device (PLD), said method comprising the steps of:
 A. providing a shadow storage unit for each internal node whose logic state is to be observed and controlled;  
 B. coupling said shadow storage unit to its respective internal node by a selective coupling circuit;  
 C. providing a data path from PLD input/output terminals to said shadow storage unit; and  
 D. observing a logic state of an internal node by: 
 i. transferring a logic state of said internal node into its respective shadow storage unit in a sample mode, and  
 ii. transferring said logic state from said shadow storage unit to a PLD I/O terminal via said data path in an observe mode.  
 
 
     
     
       6. The method of  claim 5  further comprising the steps of:
 FE. controlling a logic state of an internal node by: 
 i. pre-loading external data from a PLD I/O terminal into a shadow storage unit coupled to said internal node in a pre-load mode; and    ii. applying said external data to said internal node in a load mode.    
 
     
     
       7. A method of determining the contents of a memory block in a programmable logic device, the method comprising:
   in the memory block, providing a plurality of memory storage cells and a corresponding plurality of shadow cells;        writing data to at least one of the plurality of memory storage cells;        storing data in the plurality of memory storage cells;        transferring the data stored in the plurality of memory storage cells to the corresponding plurality of shadow cells;        storing the transferred data in the plurality of shadow cells; and        reading the data stored in the plurality of shadow cells,        wherein the transferring of the data is done by a corresponding plurality of transfer circuits, and        wherein each of the plurality of memory storage cells comprises a first inverter and a second inverter, an input of the first inverter coupled to an output of the second inverter, an output of the first inverter coupled to an input of the second inverter, and wherein each shadow cell comprises a third inverter and a fourth inverter, an input of the third inverter coupled to an output of the fourth inverter, an output of the third inverter coupled to an input of the fourth inverter.     
     
     
       8. The method of  claim 7  wherein each of the plurality of transfer circuits comprises:
   a first device coupled between a first node and a first reference voltage, having a control node coupled to the input of the first inverter;        a second device coupled between the first node and the input of the third inverter, having a control node coupled to a control line;        a third device coupled between a second node and the first reference voltage, having a control node coupled to the input of the second inverter; and        a fourth device coupled between the second node and the input of the fourth inverter, having a control node coupled to the control line.     
     
     
       9. The method of  claim 8  wherein when the control line is asserted, the data is transferred from the plurality of memory storage cells to the corresponding plurality of shadow cells. 
     
     
       10. A method of initializing a memory block in a programmable logic device, the method comprising:
   in the memory block, providing a plurality of shadow cells and a corresponding plurality of memory storage cells;        writing data to at least one of the plurality of shadow cells;        storing data in the plurality of shadow cells;        transferring the data stored in the plurality of shadow cells to the corresponding plurality of memory storage cells; and        storing the transferred data in the plurality of memory storage cells,        wherein the transferring of the data is done by a corresponding plurality of transfer circuits, and        wherein each of the plurality of memory storage cells comprises a first inverter and a second inverter, an input of the first inverter coupled to an output of the second inverter, an output of the first inverter coupled to an input of the second inverter, and wherein each shadow cell comprises a third inverter and a fourth inverter, an input of the third inverter coupled to an output of the fourth inverter, an output of the third inverter coupled to an input of the fourth inverter.     
     
     
       11. The method of  claim 10  wherein each of the plurality of transfer circuits comprises:
   a first device coupled between a first node and a first reference voltage, having a control node coupled to the input of the third inverter;        a second device coupled between the first node and the input of the first inverter, having a control node coupled to a control line;        a third device coupled between a second node and the first reference voltage, having a control node coupled to the input of the fourth inverter; and        a fourth device coupled between the second node and the input of the second inverter, having a control node coupled to the control line.     
     
     
       12. The method of  claim 11  wherein when the control line is asserted, the data is transferred from the plurality of shadow cells to the corresponding plurality of memory storage cells. 
     
     
       13. A programmable logic device comprising:
   a logic element, programmably configurable to implement user - defined combinatorial or registered logic functions; and        a memory block to store data, programmably coupled to the logic element, wherein the memory block comprises a plurality of memory cells, each memory cell comprising:      a memory storage cell to store a first data bit;        a shadow cell to store a second data bit; and        a transfer circuit, wherein when a first control line of the transfer circuit is asserted the second bit is transferred from the shadow cell to the memory storage cell, and when a second control line of the transfer circuit is asserted the first bit is transferred from the memory storage cell to the shadow cell.       
     
     
       14. The programmable logic device of  claim 13  wherein the memory block further comprises:
   a first pass device to write to the memory storage cell;        a first inverter to read from the memory storage cell;        a second pass device to write to the shadow cell; and        a second inverter to read from the shadow cell.     
     
     
       15. The programmable logic device of  claim 14  wherein the memory storage cell comprises a first inverter and a second inverter, the first inverter to receive an output from the second inverter, the second inverter to receive an output from the first inverter, and wherein the shadow cell comprises a third inverter and a fourth inverter, the third inverter to receive an output from the fourth inverter, the fourth inverter to receive an output from the third inverter. 
     
     
       16. The programmable logic device of  claim 15  wherein the content of the memory storage cell is initialized by writing to the shadow cell with the second pass device and asserting the first control line. 
     
     
       17. The programmable logic device of  claim 15  wherein the content of the shadow cell is determined by asserting the second control line, and reading the shadow cell with the second inverter. 
     
     
       18. The programmable logic device of  claim 15  wherein the transfer circuit comprises:
   a first device coupled between a first node and a first reference voltage, having a control node coupled to the input of the first inverter;        a second device coupled between the first node and the input of the third inverter, having a control node coupled to the second control line;        a third device coupled between a second node and the first reference voltage, having a control node coupled to the input of the second inverter;        a fourth device coupled between the second node and the input of the fourth inverter, having a control node coupled to the second control line;        a fifth device coupled between a third node and a first reference voltage, having a control node coupled to the input of the third inverter;        a sixth device coupled between the third node and the input of the first inverter, having a control node coupled to the first control line;        a seventh device coupled between a fourth node and the first reference voltage, having a control node coupled to the input of the fourth inverter; and        a eighth device coupled between the fourth node and the input of the second inverter, having a control node coupled to the first control line.     
     
     
       19. A programmable logic device comprising:
   a logic element, programmably configurable to implement user - defined combinatorial or registered logic functions; and        a memory block to store data, programmably coupled to the logic element, wherein the memory block comprises:      a pass device;        a memory storage cell to store data coupled to the pass device;        a transfer circuit coupled to the memory storage cell;        a shadow cell to store data coupled to the transfer circuit; and        a inverter coupled to the shadow cell,          wherein the transfer circuit selectively transfers data from the memory storage cell to the shadow cell or from the shadow cell to the memory storage cell, and        wherein data is transferred from the shadow cell to the memory cell under control of a first control line, and data is transferred from the memory storage cell to the shadow cell under control of a second control line.     
     
     
       20. The programmable logic device of  claim 19  wherein the content of the memory storage cell is initialized by writing to the shadow cell with the pass device and asserting the first control line, and wherein the content of the shadow cell is determined by asserting the second control line, and reading the shadow cell with the inverter. 
     
     
       21. The programmable logic device of  claim 20  wherein the memory storage cell comprises a first inverter and a second inverter, an input of the first inverter coupled to an output of the second inverter, an output of the first inverter coupled to an input of the second inverter, and wherein the shadow cell comprises a third inverter and a fourth inverter, an input of the third inverter coupled to an output of the fourth inverter, an output of the third inverter coupled to an input of the fourth inverter. 
     
     
       22. The programmable logic device of  claim 21  wherein the transfer circuit comprises:
   a first device coupled between a first node and a first reference voltage, having a control node coupled to the input of the first inverter;        a second device coupled between the first node and the input of the third inverter, having a control node coupled to the second control line;        a third device coupled between a second node and the first reference voltage, having a control node coupled to the input of the second inverter;        a fourth device coupled between the second node and input of the fourth inverter, having a control node coupled to the second control line;        a fifth device coupled between a third node and a first reference voltage, having a control node coupled to the input of the third inverter;        a sixth device coupled between the third node and the input of the first inverter, having a control node coupled to the first control line;        a seventh device coupled between a fourth node and the first reference voltage, having a control node coupled to the input of the fourth inverter; and        a eighth device coupled between the fourth node and the input of the second inverter, having a control node coupled to the first control line.     
     
     
       23. An integrated circuit comprising:
   a memory storage cell;        a shadow cell;        a first transfer device coupled between a first write data port line and the memory storage cell;        a second transfer device coupled between a first read data port line and the memory storage cell;        a third transfer device coupled between a first shadow data line and the shadow cell;        a first device coupled between the shadow cell and a first node; and        a second device coupled between the first node and a fixed voltage potential, wherein a control electrode of the second device is coupled to the memory storage cell.     
     
     
       24. The integrated circuit of  claim 23  further comprising:
   a fourth transfer device coupled between the first shadow data line and the shadow cell.     
     
     
       25. The integrated circuit of  claim 24  wherein the memory storage cell comprises a first inverter and a second inverter, an input of the first inverter coupled to an output of the second inverter, an output of the first inverter coupled to an input of the second inverter, and wherein the shadow cell comprises a third inverter and a fourth inverter, an input of the third inverter coupled to an output of the fourth inverter, an output of the third inverter coupled to an input of the fourth inverter. 
     
     
       26. The integrated circuit of  claim 24  wherein the first shadow data line, the first write data port line, and the first read data port line are different lines. 
     
     
       27. The integrated circuit of  claim 23  wherein data may be written to the memory storage cell using the first write data port line, but data may not be directly written to the shadow cell using the first write data port line. 
     
     
       28. The integrated circuit of  claim 23  wherein data may be written to the shadow cell using the first shadow data line, but data may not be directly written to the memory storage cell using the first shadow data line. 
     
     
       29. The integrated circuit of  claim 23  further comprising:
   a third device coupled between the memory storage cell and a second node; and        a fourth device coupled between the second node and the fixed voltage potential, wherein a control electrode of the fourth device is coupled to the shadow cell.     
     
     
       30. The integrated circuit of  claim 23  wherein the fixed voltage potential is ground. 
     
     
       31. The integrated circuit of  claim 23  wherein the first transfer device, second transfer device, and third transfer devices are NMOS transistors. 
     
     
       32. The integrated circuit of  claim 23  wherein data stored in the memory storage cell cannot be transferred directly to the first shadow data line without first passing through the shadow cell. 
     
     
       33. An integrated circuit comprising:
   a memory storage cell;        a shadow cell;        a first transfer device coupled between a first write data port line and the memory storage cell;        a second transfer device coupled between a first read data port line and the memory storage cell;        a third transfer device coupled between a first shadow data line and the shadow cell;        a first device coupled between the memory storage cell and a first node; and        a second device coupled between the first node and a fixed voltage potential, wherein a control electrode of the second device is coupled to the shadow cell.     
     
     
       34. The integrated circuit of  claim 33  further comprising:
   a fourth transfer device coupled between the first shadow data line and the shadow cell.     
     
     
       35. The integrated circuit of  claim 34  wherein the memory storage cell comprises a first inverter and a second inverter, an input of the first inverter coupled to an output of the second inverter, an output of the first inverter coupled to an input of the second inverter, and wherein the shadow cell comprises a third inverter and a fourth inverter, an input of the third inverter coupled to an output of the fourth inverter, an output of the third inverter coupled to an input of the fourth inverter. 
     
     
       36. The integrated circuit of  claim 34  wherein the first shadow data line, the first write data port line, and the first read data port line are different lines. 
     
     
       37. The integrated circuit of  claim 33  wherein data may be written to the memory storage cell using the first write data port line, but data may not be directly written to the shadow cell using the first write data port line. 
     
     
       38. The integrated circuit of  claim 33  wherein data may be written to the shadow cell using the first shadow data line, but data may not be directly written to the memory storage cell using the first shadow data line. 
     
     
       39. The integrated circuit of  claim 33  further comprising:
   a third device coupled between the shadow cell and a second node; and        a fourth device coupled between the second node and the fixed voltage potential, wherein a control electrode of the fourth transistor is coupled to the memory storage cell.     
     
     
       40. The integrated circuit of  claim 33  wherein the fixed voltage potential is ground. 
     
     
       41. The integrated circuit of  claim 33  wherein the first transfer device, second transfer device, and third transfer devices are NMOS transistors. 
     
     
       42. The integrated circuit of  claim 33  wherein data placed at the first shadow data line cannot be transferred directly to the memory storage cell without passing through the shadow cell. 
     
     
       43. The memory cell of  claim 44  wherein the first data line and the second data line are different lines. 
     
     
       44. A memory cell comprising:
   a first storage cell;        a first transfer device coupled between a first data line and the first storage cell;        a second storage cell;        a second transfer device coupled between a second data line and the second storage cell; and        a plurality of devices coupled in series between the first storage cell and a fixed voltage potential, the plurality of devices comprising:      a first device; and        a second device coupled to the first device, wherein a control electrode of the second device is coupled to the second storage cell,          wherein data placed at the second data line cannot be transferred directly to the first storage cell without passing through the second storage cell.     
     
     
       45. The memory cell of  claim 44  wherein the fixed voltage is ground. 
     
     
       46. The memory cell of  claim 44  wherein the first storage cell is a shadow cell. 
     
     
       47. The memory cell of  claim 44  wherein the second storage cell is a shadow cell. 
     
     
       48. The memory cell of  claim 44  wherein the first, and second transfer devices are NMOS devices. 
     
     
       49. The memory cell of  claim 44  wherein the first device is coupled to the first storage cell. 
     
     
       50. The memory cell of  claim 44  wherein the second device is coupled to the fixed voltage potential. 
     
     
       51. The memory cell of  claim 44  wherein the first and second devices are NMOS transistors. 
     
     
       52. The memory cell of  claim 44  wherein the first storage device comprises cross- coupled inverters.