Common source EEPROM and flash memory

Abstract

A nonvolatile memory array is arranged as a plurality of rows and columns of memory cell transistors. The sources of the memory cell transistors in each row of the array are electrically coupled together. The control gates of the memory cell transistors associated with a row in the array are coupled to a wordline associated with that row. The drains of the memory cell transistors in a column of the array are coupled to a bitline associated with that column. A source transistor is associated with each row and has its source coupled to a common source line, its drain coupled to the sources of all memory cell transistors in that row, and a gate coupled to the wordline. An array of split-gate nonvolatile memory cells is also disclosed.

1. An array of nonvolatile memory cells arranged in a plurality of rows a plurality of columns comprising:
 a substrate upon which said array is deposited;  
 a wordline plurality of wordlines wherein each of said plurality of wordlines is associated with a one of said plurality of rows in the array;  
 a plurality of bitlines wherein each of said plurality of bitlines is associated with one of said plurality of columns in the array;  
 a plurality of nonvolatile memory transistors, each of said nonvolatile memory transistors associated with a one of said plurality of rows and a one of said plurality of columns in the array, each one of said plurality of nonvolatile memory transistors having a source, a drain, a floating gate and a control gate, the control gate of each one of said plurality of nonvolatile memory transistors coupled to the one of said plurality of wordlines of said one of said plurality of rows associated with said one of said plurality of nonvolatile memory transistor, the drain of each one of said plurality of nonvolatile memory transistors coupled to the one of said plurality of bitlines of said one of said plurality of columns associated with said one of said plurality of nonvolatile memory transistors, the source of each one of said plurality of nonvolatile memory being couple to the source of each of said other ones of said plurality of nonvolatile memory transistors in said one of said plurality of rows associated with said one of said plurality of nonvolatile memory transistors;  
 a plurality of source transistors wherein each one of said plurality of source transistors has a gate coupled to a one of said plurality of wordlines, a source coupled to a source potential line, and a drain coupled to the sources of each of said plurality of nonvolatile memory transistors associated with said one of said plurality of rows associated with said wordline coupled to said source of said one of said plurality of source transistors;  
 a plurality of isolation well in said substrate wherein a portion of said plurality of nonvolatile memory transistors associated with a byte of data are disposed in each of said plurality of isolation wells; and  
 a plurality of well selection transistors wherein each one of said plurality of well selection transistors is connected to a one of said plurality of isolation wells.  
 
     
     
       2. An array of nonvolatile memory cells arranged in a plurality of rows and a plurality of columns comprising:
 a substrate upon which said array is deposited;  
 a plurality of wordlines wherein each of said plurality of wordlines is associated with a one of said plurality of rows in the array;  
 a plurality of bitlines wherein each of said plurality of bitlines is associated with one of said plurality of columns in the array;  
 a plurality of nonvolatile memory transistors, each of said nonvolatile memory transistors associated with a one of said plurality of rows and a one of said plurality of columns in the array, each one of said plurality of nonvolatile memory transistors having a source, a drain, a floating gate and a control gate, the control gate of each one of said plurality of nonvolatile memory transistors coupled to the one of said plurality of wordlines of said one of said plurality of rows associated with said one of said plurality of nonvolatile memory transistor, the drain of each one of said plurality of nonvolatile memory transistors coupled to the one of said plurality of bitlines of said one of said plurality of columns associated with said one of said plurality of nonvolatile memory transistors, the source of each one of said plurality of nonvolatile memory being couple to the source of each of said other ones of said plurality of nonvolatile memory transistors in said one of said plurality of rows associated with said one of said plurality of nonvolatile memory transistors;  
 a plurality of source transistors wherein each one of said plurality of source transistors has a gate coupled to a one of said plurality of wordlines a source coupled to a source potential line, and a drain coupled to the sources of each of said plurality of nonvolatile memory transistors associated with said one of said plurality of rows associated with said wordline coupled to said source of said one of said plurality of source transistors;  
 a plurality of isolation wells in said substrate wherein a portion of said plurality of nonvolatile memory transistors associated with a byte of data are disposed in each of said plurality of isolation wells; and  
 a plurality of well selection transistors wherein each one of said plurality of well selection transistors is connected to a one of said plurality of isolation wells.  
 
     
     
       3. An array of one-time programmable nonvolatile memory cells arranged in a plurality of rows and a plurality of columns comprising:
 a substrate upon which said array is deposited;  
 a plurality of wordlines wherein each of said plurality of wordlines is associated with a one of said plurality of rows in the array;  
 a plurality of bitlines wherein each of said plurality of bitlines is associated with one of said plurality of columns in the array;  
 a plurality of nonvolatile memory transistors, each of said nonvolatile memory transistors associated with a one of said plurality of rows and a one of said plurality of columns in the array, each one of said plurality of nonvolatile memory transistors having a source, a drain, a floating gate and a control gate, the control gate of each one of said plurality of nonvolatile memory transistors coupled to the one of said plurality of wordlines of said one of said plurality of rows associated with said one of said plurality of nonvolatile memory transistor, the drain of each one of said plurality of nonvolatile memory transistors coupled to the one of said plurality of bitlines of said one of said plurality of columns associated with said one of said plurality of nonvolatile memory transistors, the source of each one of said plurality of nonvolatile memory being couple to the source of each of said other ones of said plurality of nonvolatile memory transistors in said one of said plurality of rows associated with said one of said plurality of nonvolatile memory transistors;  
 a plurality of source transistors wherein each one of said plurality of source transistors has a gate coupled to a one of said plurality of, a source coupled to a source potential line, and a drain coupled to the sources of each of said plurality of nonvolatile memory transistors associated with said one of said plurality of rows associated with said wordline coupled to said source of said one of said plurality of source transistors;  
 a plurality of isolation well in said substrate wherein a portion of said plurality of nonvolatile memory transistors associated with a byte of data are disposed in each of said plurality of isolation wells; and  
 a plurality of well selection transistors wherein each one of said plurality of well selection transistors is connected to a one of said plurality of isolation wells.  
 
     
     
       4. A substrate, comprising:
   a plurality of nonvolatile memory metal oxide semiconductor  ( MOS )  transistors formed in rows and columns of an array;        a plurality of wordlines, one or more of said wordlines being associated with one or more of said rows;        a plurality of isolation wells, wherein one or more portions of said plurality of nonvolatile memory MOS transistors associated with one or more portions of data are disposed in associated one or more of said plurality of isolation wells;        a plurality of well selection transistors connected to associated ones of said plurality of isolation wells; and        a plurality of source transistors, one or more of said source transistors comprising gates coupled to associated one or more of said plurality of wordlines, said source transistors comprising sources coupled to a source potential line.     
     
     
       5. The substrate of  claim 4  and further comprising a plurality of bitlines, one or more of said bitlines being associated with one or more of said columns. 
     
     
       6. The substrate of  claim 5 , wherein one or more of said nonvolatile memory MOS transistors comprise a drain coupled to associated ones of said bitlines. 
     
     
       7. The substrate of  claim 4 , wherein said nonvolatile memory MOS transistors further comprise a source, wherein a source of a nonvolatile memory MOS transistor in a row is coupled to sources of other nonvolatile memory MOS transistors in said row. 
     
     
       8. The substrate of  claim 4 , wherein one or more of said nonvolatile memory MOS transistors comprise a control gate coupled to an associated one of said wordlines. 
     
     
       9. The substrate of  claim 4 , wherein one or more of said plurality of source transistors further comprise a drain coupled to sources of nonvolatile memory MOS transistors associated with a row of said one or more of said plurality of rows associated with said associated one or more wordlines. 
     
     
       10. The substrate of  claim 4 , wherein said array comprises a stacked array. 
     
     
       11. The substrate of  claim 4 , wherein said array comprises a split gate array. 
     
     
       12. The substrate of  claim 4 , wherein said non- volatile memory MOS transistors are capable of being erased using substantially a uniform channel erase.   
     
     
       13. The substrate of  claim 4 , wherein said one or more portions of data comprise one or more bytes of data. 
     
     
       14. The substrate of  claim 5 , wherein said isolation wells comprise a plurality of N- wells.   
     
     
       15. The substrate of  claim 5 , wherein said isolation wells comprise a plurality of P- wells.   
     
     
       16. A method comprising:
   forming a plurality of nonvolatile memory metal oxide semiconductor  ( MOS )  transistors in a substrate as an array comprising rows and columns;        forming a plurality of wordlines in said substrate, one or more of said wordlines being associated with one or more of said rows;        forming a plurality of isolation wells in said substrate, wherein one or more portions of said plurality of nonvolatile memory transistors are associated with one or more portions of data and disposed in associated one or more of said plurality of isolation wells;        forming a plurality of well selection transistors in said substrate connected to associated ones of said plurality of isolation wells; and        forming a plurality of source transistors in said substrate, one or more of said source transistors comprising gates coupled to associated one or more of said plurality of wordlines, said source transistors comprising sources coupled to a source potential line.     
     
     
       17. The method of  claim 16 , and further comprising forming a plurality of bitlines in said substrate, one or more of said bitlines being associated with one or more of said columns. 
     
     
       18. The method of  claim 17 , wherein one or more of said nonvolatile memory MOS transistors comprise a drain coupled to associated ones of said bitlines. 
     
     
       19. The method of  claim 16 , wherein said nonvolatile memory MOS transistors further comprise a source, wherein a source of a nonvolatile memory MOS transistor in a row is coupled to sources of other nonvolatile memory MOS transistors in said row. 
     
     
       20. The method of  claim 16 , wherein one or more of said nonvolatile memory MOS transistors comprise a control gate coupled to an associated one of said wordlines. 
     
     
       21. The method of  claim 16 , wherein one or more of said source transistors further comprises a drain coupled to sources of nonvolatile memory MOS transistors associated with a row of said one of said plurality of rows associated with said wordlines coupled to said sources of said one or more of said plurality of source transistors. 
     
     
       22. The method of  claim 16 , wherein said array comprises a stacked array. 
     
     
       23. The method of  claim 16 , wherein said array comprises a split gate array. 
     
     
       24. The method of  claim 16 , wherein said non- volatile memory MOS transistors are capable of being erased using substantially a uniform channel erase.   
     
     
       25. The method of  claim 16 , wherein said one or more portions of data comprise one or more bytes of data. 
     
     
       26. The method of  claim 16 , wherein said forming said plurality of said isolation wells further comprises forming said plurality of isolation wells in said substrate as a plurality of N- wells.   
     
     
       27. The method of  claim 16 , wherein said forming said plurality of said isolation wells further comprises forming said plurality of isolation wells in said substrate as a plurality of P- wells.   
     
     
       28. A nonvolatile memory apparatus comprising:
   a plurality of metal oxide semiconductor  ( MOS )  transistors formed in one or more rows and in a plurality of isolation wells, wherein one or more wordlines are operatively associated with said one or more of said rows and a plurality of well selection transistors are operatively associated ones of said plurality of isolation wells; and        a plurality of source transistors, one or more of said source transistors comprising gates coupled to associated one or more of said plurality of wordlines, said source transistors comprising sources coupled to a source potential line.     
     
     
       29. The nonvolatile memory apparatus of  claim 28 , wherein said plurality of metal oxide semiconductor ( MOS )  transistors comprises a stacked array.   
     
     
       30. The nonvolatile memory apparatus of  claim 28 , wherein said plurality of metal oxide semiconductor ( MOS )  transistors comprises a split gate array.   
     
     
       31. The nonvolatile memory apparatus of  claim 28 , wherein said nonvolatile memory apparatus comprises a Flash memory device. 
     
     
       32. The nonvolatile memory apparatus of  claim 28 , wherein said nonvolatile memory apparatus comprises an erasable programmable read only memory ( EPROM )  memory device.   
     
     
       33. The nonvolatile memory apparatus of  claim 28 , wherein said nonvolatile memory apparatus comprises an electrically erasable programmable read only memory ( EEPROM )  memory device.   
     
     
       34. A method for use with a nonvolatile memory apparatus, the method comprising:
   selectively causing a source of at least one source transistor having a gate coupled to at least one wordline to electrically float; and        selectively erasing at least one memory cell comprising one or more metal oxide semiconductor  ( MOS )  transistors formed in at least one row and in at least one isolation well, wherein said at least one wordline is operatively associated with said at least one row and at least one well selection transistor is operatively associated with said at least one isolation well.     
     
     
       35. A method for use with a nonvolatile memory apparatus, the method comprising:
   selectively causing a source of at least one source transistor having a gate coupled to at least one wordline to not electrically float; and        selectively programming or reading at least one memory cell comprising one or more metal oxide semiconductor  ( MOS )  transistors formed in at least one row and in at least one isolation well, wherein said at least one wordline is operatively associated with said at least one row and at least one well selection transistor is operatively associated with said at least one isolation well.