Spacer-type thin-film polysilicon transistor for low-power memory devices

Abstract

The cross-sectional area of a thin-film transistor (TFT) is decreased in order to minimize bitline to supply leakage of the TFT. This is accomplished by utilizing a spacer etch process to manufacture a TFT having a very narrow and thin channel in a controllable manner. The spacer dimensions of the TFT may be adjusted by simply modifying the thicknesses of the poly gate and the channel poly. The channel thickness is limited by the thickness of the deposited channel polysilicon which may be as thin as approximately 300 Å to 500 Å, and the channel width of the TFT corresponds to the height of the spacer etched along the polysilicon gate of the device which may be as small as approximately 0.15 to 0.25 μm.

1. A thin-film transistor (TFT) structure having a reduced cross-sectional channel area in order to minimize bitline to supply leakage of the TFT, comprising:
 a substrate;  
 a TFT polysilicon gate formed on top of the substrate;  
 a gate oxide layer formed over the substrate and the TFT polysilicon gate;  
 a TFT polysilicon channel formed adjacent to a side of the TFT polysilicon gate, wherein the TFT polysilicon channel has a channel thickness which is limited by the thickness of a deposited channel polysilicon layer which has been selectively removed leaving only the TFT polysilicon channel and wherein the TFT polysilicon channel has a channel width that corresponds to the height of the TFT polysilicon channel etched along the TFT polysilicon gate.  
 
     
     
       2. The structure of  claim 1 , wherein the channel thickness is approximately 300 to 500 Å and the channel width is approximately 0.15 to 0.25 μm. 
     
     
       3. The structure of  claim 1 , wherein the channel thickness and the channel width of the TFT polysilicon channel are adjusted by modifying the thickness of the TFT polysilicon gate. 
     
     
       4. A thin-film transistor (TFT) structure having a reduced cross-sectional channel area in order to minimize bitline to supply leakage of the TFT, comprising:
 an isolation region adjacent to an active region;  
 a polysilicon gate region formed over the active region and a first portion of the isolation region, wherein the active region is adjacent to the first portion of the isolation region;  
 a first oxide layer formed over a first portion of the active region and over a second portion of the isolation region;  
 an opening formed in the first oxide layer over a third portion of the isolation region adjacent to an end of the polysilicon gate region;  
 a second oxide layer formed over the first oxide layer, the polysilicon gate region, and the opening formed in the first oxide layer; and  
 a TFT polysilicon channel formed in the opening of the first oxide layer adjacent to the end of the polysilicon gate region, wherein the TFT polysilicon channel has a channel thickness which is limited by the thickness of a deposited channel polysilicon layer which has been selectively removed.  
 
     
     
       5. The structure of  claim 4 , wherein the channel thickness is approximately 300 to 500 Å and a channel width of the TFT polysilicon channel is approximately 0.15 to 0.25 μm. 
     
     
       6. The structure of  claim 4 , wherein the channel thickness and the channel width of the TFT polysilicon channel are adjusted by modifying the thickness of the polysilicon gate region. 
     
     
       7. A thin- film transistor structure comprising      a substrate;        a gate disposed on the substrate;        a gate insulator layer disposed on the substrate and the gate; and        a channel formed adjacent to a side of the gate, wherein the channel has a channel thickness which is limited by the thickness of a deposited channel layer which has been selectively removed leaving only the channel and wherein the channel has a channel width that corresponds to the height of the channel etched along the gate.     
     
     
       8. The thin- film transistor structure of    claim 7    wherein the channel thickness is approximately  300  to  500  Å and the channel width is approximately  0 . 15  to  0 . 25  μm.   
     
     
       9. The thin- film transistor structure of    claim 7   , wherein the channel thickness and the channel width of the channel are adjusted by modifying the thickness of the deposited channel layer and of the gate respectively.   
     
     
       10. The thin- film transistor structure of    claim 7    wherein the channel is formed from silicon.   
     
     
       11. The thin- film transistor structure of    claim 7    wherein the channel is formed from amorphous silicon.   
     
     
       12. A thin- film transistor structure comprising:      an isolation region adjacent to an active region;        a gate region formed over the active region and a first portion of the isolation region, wherein the active region is adjacent to the first portion of the isolation region;        a first insulator layer formed over a first portion of the active region and over a second portion of the isolation region;        an opening formed in the first insulator layer over a third portion of the isolation region adjacent to an end of the gate region;        a second insulator layer formed over the first insulator layer, the gate region, and the opening formed in the first insulator layer; and        a channel formed in the opening of the first insulator layer adjacent to the end of the gate region, wherein the channel has a channel thickness which is limited by the thickness of a deposited channel layer which has been selectively removed.     
     
     
       13. The structure of  claim 12 , wherein the channel thickness is approximately  300  to  500  Å and a channel width of the channel is approximately  0 . 15  to  0 . 25  μm. 
     
     
       14. The thin- film transistor structure of    claim 12   , wherein the channel thickness and the channel width of the channel are adjusted by modifying the thickness of the deposited channel layer and of the gate respectively.   
     
     
       15. The thin- film transistor structure of    claim 12    wherein the channel is formed from silicon.   
     
     
       16. The thin- film transistor structure of    claim 12    wherein the channel is formed from amorphous silicon.   
     
     
       17. A thin- film transistor structure comprising:      a substrate;        a gate disposed on the substrate;        a gate insulator layer disposed on the substrate and the gate; and        an amorphous silicon channel formed adjacent to a side of the gate, wherein the channel has a channel thickness which is limited by the thickness of a deposited channel layer which has been selectively removed leaving only the channel.     
     
     
       18. The transistor of  claim 17  wherein the substrate comprises a semiconductor material. 
     
     
       19. The transistor of  claim 17  wherein:
   the gate has a gate height; and        the channel has a height equal or approximately equal to the gate height.     
     
     
       20. A transistor, comprising:
   an isolation region;        a gate disposed on the isolation region and having a side wall;        a gate insulator disposed on the side wall of the gate; and        an amorphous silicon channel disposed on the isolation region adjacent to the side wall of the gate, wherein the channel has a channel thickness which is limited by the thickness of a deposited channel layer which has been selectively removed leaving only the channel.     
     
     
       21. The transistor of  claim 20  wherein the isolation region comprises an insulator material. 
     
     
       22. The transistor of  claim 20  wherein:
   the gate insulator is disposed on a portion of the isolation region adjacent to the side wall of the gate; and        the channel is disposed on the gate insulator.     
     
     
       23. A semiconductor structure, comprising:
   a semiconductor substrate having an active region;        an isolation insulator disposed on the substrate adjacent to the active region;        a transistor gate disposed on the active region and on the isolation insulator and having a side wall disposed over the isolation region;        a first insulator layer disposed on the side wall of the gate; and        a channel disposed on the isolation insulator adjacent to the side wall of the gate.     
     
     
       24. The semiconductor structure of  claim 23 , further comprising a second insulator layer disposed on the gate.