Semiconductor memory device

Abstract

Successive data read access with a final address specified is detected by a command mode detecting circuit to set a command mode entry status. In the command mode entry, a command of designating an internal state is made acceptable in accordance with a predetermined external signal. Consequently, a semiconductor memory device that enters a command mode, maintaining compatibility of pins and signal timings with a conventional status memory is provided.

1. A semiconductor memory device comprising:
 mode detecting circuitry for detecting that a predetermined set of external signals are applied in a combination of specific logic states successively a plurality of times, said predetermined set of external signals including an address signal; and  
 mode setting circuitry for setting a specific mode in response to a detection signal from said mode detecting circuitry.  
 
     
     
       2. The semiconductor memory device according to  claim 1 , wherein said predetermined set of external signals includes an address signal. 
     
     
       3. The semiconductor memory device according to claim  2    1  wherein said address signal comprises a multiple of bits, and said combination of specific logic states is a combination of states of the multiple bits of said address signal designating a specific address. 
     
     
       4. The semiconductor memory device according to  claim 3 , wherein said specific address is a final address. 
     
     
       5. The semiconductor memory device according to claim  2    1 , wherein said predetermined set of external signals further includes an operation mode instruction signal. 
     
     
       6. The semiconductor memory device according to  claim 5 , wherein said operation mode instruction signal is a read instruction signal for instructing a data reading operation. 
     
     
       7. The semiconductor memory device according to  claim 1 , further comprising mode circuitry made operable in response to an output signal of said mode setting circuitry in said specific mode, said mode circuitry generating, when a prescribed external signal in said external signals satisfies a predetermined condition, a signal for designating an internal state in accordance with other signals out of said external signals when made operable. 
     
     
       8. A semiconductor memory device accessed in accordance with external signals in a normal operation mode, comprising:
 a command decoder made active in a specific mode, for decoding predetermined external signals out of said external signals and generating a signal for setting an internal state to a predetermined state when activated, said signal generated by said command decoder being a signal for designating an operation related to a standby status of said semiconductor memory device, wherein 
 said command decoder activates any of a power down mode of designating cutting off of a supply of an internal power supply voltage, a wake up mode for completing said power down mode, a reset mode for setting the internal state into an initial state, a mode of designating a data holding area in a data holding mode, and an exit mode for completing said specific mode in accordance with said predetermined external signals.  
 
 
     
     
       9. The semiconductor memory device according to  claim 8 , wherein said specific mode is designated when an access in a sequence different from an access sequence performed in said normal operation mode is made. 
     
     
       10. The semiconductor memory device according to  claim 8 , wherein said specific mode is designated when a predetermined address is accessed a predetermined number of times successively. 
     
     
       11. A semiconductor memory device accessed in accordance with external signals in a normal operation mode, comprising:
 mode detecting circuitry for detecting that a predetermined set of external signals out of said external signals are applied in a combination of specific logic states a plurality of times successively, said predetermined set of external signals including an address signal, and said mode detecting circuitry detecting that said address signal is applied in a state of designating a specific address said plurality of times;  
 mode setting circuitry for setting a specific mode in response to a detection signal of said mode detecting circuitry; and  
 mode circuitry rendered operable in said specific mode in accordance with an output signal of said mode setting circuitry.  
 
     
     
       12. The semiconductor memory device according to  claim 11 , wherein said predetermined set of external signals includes an address signal, and
 said mode detecting circuitry detects that said address signal is applied in a state of designating a specific address said predetermined number of times.    
     
     
       13. The semiconductor memory device according to  claim 11 , wherein said mode circuitry is a command decoding circuit for decoding a command constructed of said predetermined set of external signals and generating an operation mode instruction signal in accordance with a result of decoding, and
 said command decoding circuit activates either of a power down mode of designating cutting off of supply of an internal power supply voltage, a wake up mode for completing said power down mode, a reset mode for setting an internal state to an initial state, a mode of designating a data holding area in a data holding mode, and an exit mode for completing said specific mode.  
 
     
     
       14. The semiconductor memory device according to  claim 11 , wherein
 said mode circuitry generates a signal of designating an internal state in accordance with an externally applied signal in said specific mode and  
 said semiconductor memory device further comprises an internal status control circuit for setting an internal state to a state designated by an output signal of said mode circuitry in accordance with the output signal of said mode circuitry.  
 
     
     
       15. The semiconductor memory device according to  claim 14 , wherein said mode circuitry generates, when a prescribed external signal in said external signals satisfies a predetermined condition, a signal for designating said internal state in accordance with other signals out of said external signals. 
     
     
       16. The semiconductor memory device according to  claim 11 , wherein said mode circuitry generates, when a prescribed external signal in said external signals satisfies a predetermined condition, a signal for designating an internal state in accordance with other signals out of said external signals when made operable. 
     
     
       17. The semiconductor memory device according to  claim 6 , further comprising a memory cell array having a plurality of memory cells arranged in rows and columns, wherein
   the address signal includes a row address signal designating a row of said rows, and a column address signal designating a column of said columns, and        said external signals further include a chip enable signal enabling said semiconductor memory device, and an output enable signal enabling data output from said semiconductor memory device.     
     
     
       18. The semiconductor memory device according to  claim 17 , wherein said specific mode includes a power down mode of cutting off a supply of a power to internal circuitry in said semiconductor memory device. 
     
     
       19. The semiconductor memory device according to  claim 18 , wherein said specific mode further includes a wake up mode for completing said power down mode. 
     
     
       20. The semiconductor memory device according to  claim 17 , wherein said specific mode further includes a reset mode for setting internal circuitry in said semiconductor device to an initial state. 
     
     
       21. The semiconductor memory device according to  claim 17 , wherein said specific mode further includes a mode for designating a data holding region in said memory cell array in a data holding mode for holding storage data. 
     
     
       22. The semiconductor memory device according to  claim 17 , wherein said specific mode further includes an exit mode for completing a set operation mode. 
     
     
       23. The semiconductor memory device according to  claim 17 , wherein data communicated externally with said semiconductor memory device include an upper byte data and a lower byte data, and
   invalidation and validation of said upper byte data are controlled by an upper byte enable signal and invalidation and validation of said lower byte data is controlled by an upper byte enable signal.     
     
     
       24. The semiconductor memory device according to  claim 23 , further comprising mode circuitry made operable in said specific mode in accordance with an output signal of said mode setting circuitry, said mode circuitry generating a signal designating an internal state in said specific mode in accordance with external signals, and generating said signal designating said internal state in accordance with the external signals including said upper byte data and said lower byte data, whichever is made valid, when a predetermined signal out of the external signals satisfies a prescribed condition. 
     
     
       25. The semiconductor memory device according to  claim 11 , wherein said specific address is a final address. 
     
     
       26. The semiconductor memory device according to  claim 25 , further comprising a memory cell array having a plurality of memory cells arranged in rows and columns, wherein
   said address signal includes a row address signal designating a row of said rows, and a column address signal designating a column of said columns, and        the external signals include a chip enable signal enabling said semiconductor memory device and an output enable signal enabling output of data from said semiconductor memory device.     
     
     
       27. The semiconductor memory device according to  claim 26 , wherein said specific mode includes a power down mode for cutting off a supply of a power to said semiconductor memory device. 
     
     
       28. The semiconductor memory device according to  claim 27 , wherein said specific mode further includes a wake up mode for completing said power down mode. 
     
     
       29. The semiconductor memory device according to  claim 26 , wherein said specific mode further includes a reset mode for setting an internal state of said semiconductor memory device to an initial state. 
     
     
       30. The semiconductor memory device according to  claim 26 , wherein said specific mode further includes a mode for designating a data holding region in said memory cell array for holding storage data in a data holding mode. 
     
     
       31. The semiconductor memory device according to  claim 26  wherein said specific mode further includes an exit mode for completing a set mode.