CAM arrays having CAM cells therein with match line and low match line connections and methods of operating same

Abstract

A CAM array including volatile or non-volatile ternary CAM cells that discharge their associated match line through a special discharge line (e.g., a low match line), instead of through the bit line, is disclosed. Each ternary CAM cell includes a pair of storage elements that are used to store a data bit value, a comparison element that is used to compare the stored value with an applied data value, and a discharge element that is coupled between the discharge line and the match line. During operation, when the applied data value matches the stored value, the discharge element de-couples the discharge line from the match line (i.e., a high voltage on the match line remains high). Conversely, when the applied data value does not match the stored value, the discharge elements couple the discharge line to the match line, thereby discharging the match line to the discharge line. By discharging the match line to the discharge line instead of the bit lines of the CAM array, the size of the CAM array is not limited by the length bit lines. Because the voltage on the match line is sensed to determine the match/no-match condition of a CAM cell, the match line does not need to be completely discharged.

1. A content-addressable memory (CAM) array comprising:
 a bit line;  
 a word line;  
 a match line;  
 a discharge line;  
 a content-addressable memory (CAM) cell including: 
 means coupled to the bit line and the word line for storing a first data value during a set-up phase, and  
 a comparison circuit coupled between the match line and the discharge line for comparing the stored value received from the storage circuit with an applied data value and for connecting the match line to the discharge line if the stored value is different from the data value; and  
 
 a control circuit coupled to the discharge line for applying a first voltage to the discharge line during the set-up phase, and for applying a second voltage to the discharge line during the comparison phase.  
 
     
     
       2. An integrated circuit including a bit line, a word line, a match line, a discharge line, and a content-addressable memory (CAM) cell, the CAM cell comprising:
 a first volatile transistor having a first terminal coupled to the bit line, a second terminal, and a gate terminal coupled to the word line;  
 a second volatile transistor having a first terminal coupled to receive a data signal, a second terminal, and a gate terminal coupled to the second terminal of the first volatile transistor; and  
 a third volatile transistor having a first terminal coupled to the match line, a second terminal coupled to the discharge line, and a gate terminal coupled to the second terminal of the second volatile transistor; 
 wherein the third volatile transistor is turned on to shunt the match line to the discharge line when the bit line, the word line, and the data signal received by the second volatile transistor are high during a predetermined time period.  
 
 
     
     
       3. A ternary content addressable memory (CAM) cell comprising:
 a first storage element;  
 a second storage element;  
 a first access transistor having a first terminal coupled to the first storage element, a second terminal, and a gate terminal;  
 a first word line coupled to the gate terminal of the first access transistor;  
 a first bit line coupled to the second terminal of the first access transistor;  
 a second access transistor having a first terminal coupled to the second storage element, a second terminal, and a gate terminal;  
 a second word line coupled to the gate terminal of the second access transistor;  
 a second bit line coupled to the second terminal of the second access transistor;  
 a first comparison transistor having a gate terminal coupled to the first storage element, a first terminal and a second terminal;  
 a first data line coupled to the first terminal of the first comparison transistor;  
 a second comparison transistor having a gate terminal coupled to the second storage element, a first terminal and a second terminal;  
 a second data line coupled to the first terminal of the second comparison transistor;  
 a third comparison transistor having a gate terminal coupled to the second terminal of the first comparison transistor and coupled to the second terminal of the second comparison transistor, a first terminal and a second terminal;  
 a match line coupled to the first terminal of the third comparison transistor; and  
 a low match line coupled to the second terminal of the third comparison transistor.  
 
     
     
       4. The ternary CAM cell of  claim 3 , wherein the first storage element comprises a wire. 
     
     
       5. The ternary CAM cell of  claim 3 , wherein the first storage element comprises a first capacitor. 
     
     
       6. The ternary CAM cell of  claim 5 , wherein the second storage element comprises a second capacitor. 
     
     
       7. The ternary CAM cell of  claim 6 , wherein a plate of the first capacitor is coupled to a plate of the second capacitor. 
     
     
       8. The ternary CAM cell of  claim 6 , wherein a first voltage source is coupled between the first capacitor and the second capacitor. 
     
     
       9. The ternary CAM cell of  claim 3 , wherein the first bit line is co-formed with the first data line and the second bit line is co-formed with the second data line. 
     
     
       10. The ternary CAM cell of  claim 3 , wherein the first word line is co-formed with the second word line. 
     
     
       11. The ternary CAM cell of  claim 3 , wherein the low match line comprises a voltage controlling circuit. 
     
     
       12. The ternary CAM cell of  claim 3 , wherein the low match line is coupled to a ground. 
     
     
       13. A ternary content addressable memory (CAM) cell comprising:
 a first storage element;  
 a second storage element;  
 a first access transistor having a first terminal coupled to the first storage element, a second terminal, and a gate terminal;  
 a first word line coupled to the gate terminal of the first access transistor;  
 a first bit line coupled to the second terminal of the first access transistor;  
 a second access transistor having a first terminal coupled to the second storage element, a second terminal, and a gate terminal;  
 a second word line coupled to the gate terminal of the second access transistor;  
 a second bit line coupled to the second terminal of the second access transistor;  
 a first comparison transistor having a gate terminal coupled to the first storage element, a first terminal and a second terminal;  
 a second comparison transistor having a first terminal coupled to the first terminal of the first comparison transistor, a second terminal and a gate terminal;  
 a first data line coupled to the gate terminal of the second comparison transistor;  
 a third comparison transistor having a gate terminal coupled to the second storage element, a first terminal, and a second terminal;  
 a fourth comparison transistor having a first terminal coupled to a drain of the third comparison transistor, a second terminal, and a gate terminal;  
 a second data line coupled to the gate terminal of the fourth comparison transistor;  
 a match line coupled to the second terminal of the first comparison transistor and to the second terminal of the third comparison transistor; and  
 a low match line coupled to the second terminal of the second comparison transistor and to the second terminal of the fourth comparison transistor.  
 
     
     
       14. The ternary CAM cell of  claim 13 , wherein the first storage element comprises a wire. 
     
     
       15. The ternary CAM cell of  claim 13 , wherein the first storage element comprises a first capacitor. 
     
     
       16. The ternary CAM cell of  claim 15 , wherein the second storage element comprises a second capacitor. 
     
     
       17. The ternary CAM cell of  claim 16 , wherein a plate of the first capacitor is coupled to a plate of the second capacitor. 
     
     
       18. The ternary CAM cell of  claim 16 , wherein a first voltage source is coupled between the first capacitor and the second capacitor. 
     
     
       19. The ternary CAM cell of  claim 13 , wherein the first bit line is co-formed with the first data line, and the second bit line is co-formed with the second data line. 
     
     
       20. The ternary CAM cell of  claim 13 , wherein the first word line is co-formed with the second word line. 
     
     
       21. The ternary CAM cell of  claim 13 , wherein the low match line comprises a voltage controlling circuit. 
     
     
       22. The ternary CAM cell of  claim 13 , wherein the low match line is coupled to a ground. 
     
     
       23. A ternary content addressable memory (CAM) cell comprising:
 a first non-volatile transistor having a first terminal, a second terminal, and a gate terminal;  
 a second non-volatile transistor having a first terminal, a second terminal, and a gate terminal;  
 a first access transistor having a first terminal coupled to a gate of the first non-volatile transistor, a second terminal, and a gate terminal;  
 a first word line coupled to the gate terminal of the first access transistor;  
 a first bit line coupled to the second terminal of the first access transistor;  
 a second access transistor having a first terminal coupled to the gate terminal of the second non-volatile transistor, a second terminal, and a gate terminal;  
 a second word line coupled to the gate terminal of the second access transistor;  
 a second bit line coupled to the second terminal of the second access transistor;  
 a first comparison transistor having a first terminal coupled to the first terminal of the first non-volatile transistor, a second terminal, and a gate terminal;  
 a first data line coupled to the gate terminal of the first comparison transistor;  
 a second comparison transistor having a first terminal coupled to the first terminal of the second non-volatile transistor, a second terminal, and a gate terminal;  
 a second data line coupled to the gate terminal of the second comparison transistor;  
 a match line coupled to the second terminal of the first non-volatile transistor and to the second terminal of the second non-volatile transistor; and  
 a low match line coupled to the second terminal of the first comparison transistor and to the second terminal of the second comparison transistor.  
 
     
     
       24. The ternary CAM cell of  claim 23 , wherein the first bit line is co-formed with the first data line and the second bit line is co-formed with the second data line. 
     
     
       25. The ternary CAM cell of  claim 23 , wherein the first word line is co-formed with the second word line. 
     
     
       26. The ternary CAM cell of  claim 23 , wherein the low match line comprises a voltage controlling circuit. 
     
     
       27. The ternary CAM cell of  claim 23 , wherein the low match line is coupled to a ground. 
     
     
       28. A ternary content addressable memory (CAM) cell comprising:
 a first capacitor;  
 a second capacitor;  
 a first access transistor having a first terminal coupled to a first plate of the first capacitor, a second terminal, and a gate terminal;  
 a first word line coupled to the gate terminal of the first access transistor;  
 a first bit line coupled to the second terminal of the first access transistor;  
 a first data line coupled to a second plate of the first capacitor;  
 a second access transistor having a first terminal coupled to a first plate of the second capacitor, a second terminal, and a gate terminal;  
 a second word line coupled to the gate terminal of the second access transistor;  
 a second bit line coupled to the second terminal of the second access transistor;  
 a second data line coupled to a second plate of the second capacitor;  
 a first comparison transistor having a gate coupled to the first plate of the first capacitor;  
 a second comparison transistor having the gate terminal coupled to the second plate of the second capacitor;  
 a match line coupled to the first terminal of the first comparison transistor and to the first terminal of the second comparison transistor; and  
 a low match line coupled to the second terminal of the first comparison transistor and to the second terminal of the second comparison transistor.  
 
     
     
       29. A method of operating a CAM array including a match line, a low match line, a plurality of data lines, and a plurality of CAM cells arranged in a row, each CAM cell being connected to an associated data line and including a switch connected between the match line and the low match line, the switch being controlled by a first data value stored in said each CAM cell, the method comprising:
 during a pre-charge operation, equalizing a voltage level on the low match line with a the voltage level on the match line, thereby preventing current flow between the low match line and the match line through the switch; and    during a subsequent operation, pulling down on the voltage level on the low match line to a logic low voltage level, thereby causing the match line to discharge to the low match line.    
     
     
       30. The method of  claim 29 , wherein the subsequent operation is a read operation. 
     
     
       31. The method of  claim 29 , wherein the subsequent operation is a compare operation. 
     
     
       32. The method of  claim 29 , wherein the subsequent operation is a write operation. 
     
     
       33. A method of operating a content addressable memory ( CAM )  array, comprising the step of:      precharging a match line and low match line that are connected to a CAM cell to a logic high level; and        equalizing a potential of a data line and an inverted data line connected to the CAM cell by transferring charge from a more positively biased one of the data line and the inverted data line to a less positively biased one of the data line and the inverted data line while the match line and low match line are at a logic high level.     
     
     
       34. The method of  claim 33 , further comprising the step of:
   comparing data on the data line and the inverted data line with data stored in the CAM cell in - sync with discharging the low match line from its precharged high level.     
     
     
       35. The method of  claim 34 , wherein said comparing step is preceded by the step of driving the data line high ( or low )  from the equalized potential and driving the inverted data line low  ( or high )  from the equalized potential.   
     
     
       36. A method of operating a content addressable memory ( CAM )  cell having a comparison circuit therein that is electrically coupled to a data line, an inverted data line, a match line and a low match line, the method comprising the steps of:      storing a data value in the CAM cell during a write operation;        comparing an applied data value established across the data line and the inverted data line with the data value stored in the CAM cell during a compare operation; and        transferring charge from a more positively biased one of the data line and the inverted data line to a less positively biased one of the data line and the inverted data line during an operation that precedes or follows the compare operation.     
     
     
       37. The method of  claim 36 , wherein said comparing step is performed in response to discharging the low match line from a precharged high level. 
     
     
       38. The method of  claim 36 , wherein said transferring step comprises transferring charge from a more positively biased one of the data line and the inverted data line to a less positively biased one of the data line and the inverted data line while the match line and the low match line are being precharged to or held at a logic high level. 
     
     
       39. The method of  claim 38 , further comprising discharging the low match line from its logic high level during the compare operation. 
     
     
       40. The method of  claim 39 , wherein said comparing step is preceded by the step of driving the data line high ( or low )  and the inverted data line low  ( or high )  to represent the applied data value.   
     
     
       41. The method of  claim 36 , wherein said comparing step is preceded by the step of driving the data line high ( or low )  and the inverted data line low  ( or high )  to represent the applied data value.   
     
     
       42. A method of operating a content addressable memory ( CAM )  cell having a comparison circuit therein that is electrically coupled to a data line, an inverted data line, a match line and a low match line, the method comprising the steps of:      disabling the comparison circuit by precharging the match line to a first logic high level and precharging the low match line to a second logic high level less than Vcc during a precharge operation, where Vcc is a power supply voltage; and        enabling the comparison circuit by discharging the low match line from the second logic high level to a logic low level at a commencement of a compare operation.     
     
     
       43. The method of  claim 42 , wherein the first logic high level is less than Vcc. 
     
     
       44. The method of  claim 43 , wherein the first logic high level equals the second logic high level. 
     
     
       45. A content addressable memory ( CAM )  array, comprising:      a plurality of CAM cells;        a low match line electrically coupled to a respective comparison circuit in each of said plurality of CAM cells;        a match line electrically coupled to the respective comparison circuit in each of said plurality of CAM cells; and        a control circuit that is configured to precharge said match line to a first logic high level and precharge said low match line to a second logic high level that is less than Vcc during a precharge operation, where Vcc is a power supply voltage.     
     
     
       46. The CAM array of  claim 45 , wherein said control circuit is configured to pull- down the low match line from its precharged second logic high level upon commencement of a compare operation.   
     
     
       47. The CAM array of  claim 45 , wherein the first logic high level is less than Vcc. 
     
     
       48. The CAM array of  claim 47 , wherein the first logic high level equals the second logic high level. 
     
     
       49. A content addressable memory ( CAM )  array, comprising:      a row of CAM cells that is electrically coupled to a match line and a low match line and is configured to undergo an operation to compare an applied data word to a stored data word in said row of CAM cells in - sync with a high - to - low transition of the low match line from a logic high level that is less than Vcc to a logic low level, where Vcc is a power supply voltage.     
     
     
       50. A method of operating a content addressable memory ( CAM )  array, comprising the step of:      precharging a match line that is connected to a CAM cell to a first logic high level and a low match line that is connected to the CAM cell to a second logic high level that is less than Vcc during a precharge operation, where Vcc is a power supply voltage;        equalizing a potential of a data line and an inverted data line connected to the CAM cell by transferring charge from a more positively biased one of the data line and the inverted data line to a less positively biased one of the data line and the inverted data line while the match line and low match line are precharged; and        driving a bit line and an inverted bit line that are connected to the CAM cell with write data during a write operation.     
     
     
       51. The method of  claim 50 , wherein the first logic high level is less than Vcc. 
     
     
       52. The method of  claim 51 , wherein the first logic high level equals the second logic high level. 
     
     
       53. A method of operating a content addressable memory ( CAM )  array, comprising the step of:      precharging a match line segment that is connected to a CAM cell to a first logic high level during a precharge operation;        precharging a low match line segment that is connected to the CAM cell to a second logic high level having a maximum voltage less than Vcc during the precharge operation, where Vcc is a power supply voltage;        equalizing a potential of a data line and an inverted data line connected to the CAM cell by transferring charge from a more positively biased one of the data line and the inverted data line to a less positively biased one of the data line and the inverted data line while the match line segment and the low match line segment are precharged; and        comparing data on the data line and the inverted data line with data stored in the CAM cell in - sync with discharging the low match line segment from its precharged second logic high level to a logic low level.     
     
     
       54. The method of  claim 53 , wherein said comparing step is preceded by the step of driving the data line high ( or low )  from the equalized potential and driving the inverted data line low  ( or high )  from the equalized potential.   
     
     
       55. A content addressable memory ( CAM )  array, comprising:      a row of CAM cells that is electrically coupled to a match line segment and a low match line segment and is configured to undergo an operation to compare an applied data word to a data word stored in said row of CAM cells in - sync with a high - to - low transition of the low match line segment from a precharged logic high level, which has a maximum voltage less than Vcc, to a logic low level, where Vcc is a power supply voltage.     
     
     
       56. A method of operating a content addressable memory ( CAM )  array, comprising the step of:      precharging a match line segment that is connected to a CAM cell to a first logic high level and a low match line segment that is connected to the CAM cell to a second logic high level having a maximum voltage less than Vcc during a precharge operation, where Vcc is a power supply voltage; and        comparing data applied to the CAM cell to data stored in the CAM cell in - sync with discharging the low match line segment from the second logic high level to a logic low level.     
     
     
       57. A method of operating a content addressable memory ( CAM )  array, comprising the step of:      precharging a match line segment that is connected to a CAM cell during a precharge operation;        precharging a low match line segment that is connected to the CAM cell to a first logic high level having a maximum voltage that is less than Vcc during the precharge operation, where Vcc is a power supply voltage;        equalizing a potential of a data line and an inverted data line connected to the CAM cell by transferring charge from a more positively biased one of the data line and the inverted data line to a less positively biased one of the data line and the inverted data line while the match line segment and the low match line segment are precharged;        driving the data line and inverted data line with data by pulling up the data line to a second logic high level that exceeds the maximum voltage and pulling down the inverted data line to a logic low level, while the match line segment and the low match line segment are precharged; and        comparing the data on the data line and the inverted data line with data stored in the CAM cell in - sync with discharging the low match line segment from its precharged first logic high level to a logic low level.     
     
     
       58. A content addressable memory ( CAM )  array, comprising:      a row of CAM cells that is electrically coupled to a match line segment, a low match line segment and a plurality of pairs of differential data lines, said row configured to perform a compare operation between a search word applied to the plurality of pairs of differential data lines and data stored in said row in - sync with a high - to - low transition of the low match line segment from a precharged logic high level, which has a maximum voltage that is less than a maximum voltage on the plurality of pairs of differential data lines during the compare operation, to a logic low level.     
     
     
       59. A method of operating a content addressable memory ( CAM )  array, comprising the step of:      precharging a match line segment that is connected to a CAM cell to a first logic high level during a precharge operation;        precharging a low match line segment that is connected to the CAM cell to a second logic high level having a maximum voltage that is less than Vcc during the precharge operation, where Vcc is a power supply voltage;        driving a data line and an inverted data line that are connected to the CAM cell with data by pulling up the data line to a logic high level that exceeds the maximum voltage and pulling down the inverted data line to a logic low level, while the match line segment and the low match line segment are precharged; and        comparing data applied to the CAM cell with data stored in the CAM cell in - sync with discharging the low match line segment from the second logic high level to a logic low level.