Method for placing active circuits beneath active bonding pads

Abstract

The present invention provides a bonding pad structure for integrated circuit devices which allows the active circuits to be placed under bonding pads of the device without affecting the performance of the active circuits. The bonding pad structure is composed of at least two metal layers overlying the active circuits so that the bonding pad may be subjected to thermal and mechanical stresses without damaging the underlying active circuits. The metal layer underlying the bonding pad is patterned and etched forming an array of openings in the metal that may take any shape, e.g. slots, grid, circles. The present invention enables a reduction in the chip area and eliminates the parasitic resistance due to long interconnection wires between bonding pads and active regions.

1. A method for forming a bonding pad structure over an active circuit of an integrated circuit device, the method comprising the steps of:
 depositing at least one conductive layer directly over said active circuit,  
 depositing a metal layer directly over said active circuit after depositing said at least one conductive layer;  
 patterning and etching said metal layer to form an array of openings in said metal layer;  
 depositing a dielectric layer over said metal layer and over said array of openings in said metal layer;  
 forming one or more vias in said dielectric layer; and  
 forming a bonding pad that  directly over said active circuit and said array of openings in said metal layer, wherein said bonding pad is electrically and physically connected to said metal layer by said one or more vias.  
 
     
     
       2. The method as described in  claim 1  further comprising the step of depositing at least one conductive layer over said active circuit, wherein said step of depositing at least one conductive layer is performed prior to said step of depositing said metal layer  depositing an insulating layer over said at least one conductive layer prior to depositing said metal layer. 
     
     
       3. The method as described in  claim 1  wherein said active circuit is an electrostatic discharge circuit. 
     
     
       4. The method as described in  claim 1  wherein said active circuit comprises a circuit selected from the group consisting of: a transistor, a resistor, a capacitor, an inductor, or any combination thereof. 
     
     
       5. The method as described in  claim 1  wherein said dielectric layer comprises silicon dioxide. 
     
     
       6. The method as described in  claim 1  wherein said bonding pad comprises a material selected from the group consisting of: polysilicon, silicon alloys, aluminum, aluminum alloys, gold, gold alloys, copper, and copper alloys, or any combination thereof. 
     
     
       7. The method as described in  claim 1  wherein said metal layer comprises a material selected from the group consisting of: polysilicon, silicon alloys, aluminum, aluminum alloys, copper, and copper alloys, or any combination thereof. 
     
     
       8. The method as described in  claim 2  wherein said conductive layer comprises a material selected from the group consisting of: polysilicon, silicon alloys, aluminum, aluminum alloys, copper, and copper alloys, or any combination thereof. 
     
     
       9. The method as described in  claim 1  wherein said step of patterning and etching said metal layer forms a conductive region taking the shape of a grid. 
     
     
       10. The method as described in  claim 1  wherein said step of patterning and etching said metal layer forms a conductive region taking the shape of a waffle. 
     
     
       11. The method as described in  claim 1  wherein said step of patterning and etching said metal layer forms metal slots. 
     
     
       12. The method as described in  claim 1  wherein said bonding pad is connected to said active circuit by a via  one or more vias are located along the  an edge of said bonding pad. 
     
     
       13. A method for forming a bonding pad structure over an active circuit of an integrated circuit device, the method comprising the steps of:
 depositing a plurality of metal layers directly over said active circuit, wherein said plurality of metal layers has an uppermost metal layer;  
 patterning and etching said uppermost metal layer to form an array of openings in said uppermost metal layer;  
 depositing a dielectric layer over said uppermost metal layer and over said array of openings in said uppermost metal layer;  
 forming one or more vias in said dielectric layer; and  
 forming a bonding pad that  directly over said active circuit and said array of openings in said uppermost layer, wherein said bonding pad is electrically and physically connected to said uppermost metal layer by said one or more vias.  
 
     
     
       14. The method as described in  claim 13  wherein said active circuit is an electrostatic discharge circuit. 
     
     
       15. The method as described in  claim 13  wherein said active circuit comprises a circuit selected from the group consisting of: a transistor, a resistor, a capacitor, an inductor, or any combination thereof. 
     
     
       16. The method as described in  claim 13  wherein said dielectric layer comprises silicon dioxide. 
     
     
       17. The method as described in  claim 13  wherein said bonding pad comprises a material selected from the group consisting of: polysilicon, silicon alloys, aluminum, aluminum alloys, gold, gold alloys, copper, and copper alloys, or any combination thereof. 
     
     
       18. The method as described in  claim 13  wherein said metal layers comprise a material selected from the group consisting of: polysilicon, silicon alloys, aluminum, aluminum alloys, copper, and copper alloys, or any combination thereof. 
     
     
       19. The method as described in  claim 13  wherein said step of patterning and etching said uppermost metal layer forms a conductive region taking the shape of a grid. 
     
     
       20. The method as described in  claim 13  wherein said step of patterning and etching said uppermost metal layer forms a conductive region taking the shape of a waffle. 
     
     
       21. The method as described in  claim 13  wherein said step of patterning and etching said uppermost metal layer forms metal slots. 
     
     
       22. The method as described in  claim 13  wherein said bonding pad is connected to said active circuit by a via located along the edge of said bonding pad. 
     
     
       23. A method for forming a bonding pad structure over an active circuit of an integrated circuit device, the method comprising the steps of:
 depositing a plurality of metal layers directly over said active circuit, wherein said plurality of metal layers has an uppermost metal layer;  
 patterning and etching said uppermost metal layer to form an array of openings in said uppermost metal layer;  
 depositing a dielectric layer over said uppermost metal layer and over said array of openings in said uppermost metal layer;  
 forming one or more vias in said dielectric layer; and  
 forming a bonding pad directly over said active circuit and said array of openings in said uppermost metal layer, wherein said bonding pad is connected to said active circuit and said uppermost metal layer by vias located along the edge of said bonding pad.  
 
     
     
       24. The method as described in  claim 23  wherein said active circuit is an electrostatic discharge circuit. 
     
     
       25. The method as described in  claim 23  wherein said active circuit comprises a circuit selected from the group consisting of: a transistor, a resistor, a capacitor, an inductor, or any combination thereof. 
     
     
       26. The method as described in  claim 23  wherein said dielectric layer comprises silicon dioxide. 
     
     
       27. The method as described in  claim 23  wherein said bonding pad comprises a material selected from the group consisting of: polysilicon, silicon alloys, aluminum, aluminum alloys, gold, gold alloys, copper, and copper alloys, or any combination thereof. 
     
     
       28. The method as described in  claim 23  wherein said metal layers comprise a material selected from the group consisting of: polysilicon, silicon alloys, aluminum, aluminum alloys, copper, and copper alloys, or any combination thereof. 
     
     
       29. The method as described in  claim 23  wherein said step of patterning and etching said uppermost metal layer forms a conductive region taking the shape of a grid. 
     
     
       30. The method as described in  claim 23  wherein said step of patterning and etching said uppermost metal layer forms a conductive region taking the shape of a waffle. 
     
     
       31. The method as described in  claim 23  wherein said step of patterning and etching said uppermost metal layer forms metal slots. 
     
     
       32. A bonding pad structure over an active circuit of an integrated circuit device comprising:
   a plurality of metal layers directly over said active circuit, wherein said plurality of metal layers has an uppermost metal layer having an array of openings directly over said active circuit;        a bonding pad positioned directly over said active circuit and said array of openings;        an insulating layer positioned between said uppermost metal layer and said bonding pad; and        a via formed in said insulating layer physically connecting said uppermost metal layer and said bonding pad.      
     
     
       33. The bonding pad structure of  claim 32  wherein said insulating layer is formed of silicon dioxide.  
     
     
       34. The bonding pad structure of  claim 32  wherein said uppermost metal layer having an array of openings takes on the shape of a waffle.  
     
     
       35. The bonding pad structure of  claim 32  wherein said uppermost metal layer is formed from a material selected from the group consisting of: polysilicon, silicon alloys, aluminum, aluminum alloys, gold, gold alloys, copper, and copper alloys, or any combination thereof.  
     
     
       36. The bonding pad structure of  claim 32  wherein said via is located along an edge of said bonding pad.  
     
     
       37. The bonding pad structure of  claim 32  wherein said active circuit comprises a circuit selected from the group consisting of: a transistor, a resistor, a capacitor, an inductor, or any combination thereof.  
     
     
       38. The bonding pad structure of  claim 32  wherein said active circuit is an electrostatic discharge protection circuit.  
     
     
       39. The bonding pad structure of  claim 32  wherein said active circuit is formed on a substrate.  
     
     
       40. A bonding pad structure comprising:
   an active circuit;        a first insulating layer formed over said active circuit;        a plurality of metal layers directly over said active circuit, wherein said plurality of metal layers has an uppermost layer having an array of openings;        a second insulation layer formed over said uppermost metal layer;        a bonding pad formed directly over said active circuit and said array of openings; and        a via formed in said second insulating layer physically connecting said bonding pad and said uppermost metal layer.      
     
     
       41. The bonding pad structure of  claim 40  wherein said uppermost metal layer comprises a material selected from the group consisting of: polysilicon, silicon alloys, aluminum, aluminum allows, gold, gold alloys, copper, and copper alloys or any combination thereof.  
     
     
       42. The bonding pad structure of  claim 41  wherein said bonding pad comprises a material selected from the group consisting of: polysilicon, silicon alloys, aluminum, aluminum allows, gold, gold alloys, copper, and copper alloys or any combination thereof.  
     
     
       43. The bonding pad structure of  claim 41  wherein said active circuit comprises a circuit selected from the group consisting of: a transistor, a resistor, a capacitor, an inductor, or any combination thereof.  
     
     
       44. The bonding pad structure of  claim 43  wherein said uppermost metal layer having an array of openings forms a conductive region taking the shape of a waffle.  
     
     
       45. The bonding pad structure of  claim 40  wherein said uppermost metal layer and said active circuit are in electrical communication through a via.  
     
     
       46. The bonding pad structure of  claim 45  wherein said active circuit is an electrostatic discharge circuit.  
     
     
       47. The bonding pad structure of  claim 40  wherein said first insulating layer and said second insulating layer comprises silicon dioxide.  
     
     
       48. The bonding pad structure of  claim 40  wherein said array of openings forms slots in said uppermost metal layer.  
     
     
       49. A bonding pad structure comprising:
   a substrate layer having an active circuit;        a bonding pad positioned directly over said active circuit;        an intermediary layer having a plurality of metal layers and a plurality of insulating layers directly over said active circuit, each one of said plurality of metal layers covered by one of said plurality of insulating layers, at least one of said plurality of metal layers containing an array of openings that form a grid and being in electrical and physical contact with said bonding pad through a via.      
     
     
       50. The bonding pad structure of  claim 49  wherein said plurality of metal layers comprise a material selected from the group consisting of: polysilicon, silicon alloys, aluminum, aluminum alloys, gold alloys, copper, and copper alloys or any combination thereof.  
     
     
       51. The bonding pad structure of  claim 50  wherein said active circuit comprises a circuit selected from the group consisting of: a transistor, a resistor, a capacitor, an inductor, or any combination thereof.  
     
     
       52. The bonding pad structure of  claim 49  wherein said active circuit is an electrostatic discharge circuit.  
     
     
       53. A method for forming a bonding pad structure comprising the steps of:
   forming a plurality of metal layers directly over an active circuit, wherein said plurality of metal layers includes an uppermost metal layer having an array of openings;        forming a dielectric layer over said uppermost metal layer;        forming a via in said dielectric layer; and        forming a bonding pad that is electrically and physically connected to said uppermost metal layer by said via, said bonding pad positioned directly over said active circuit and said array of openings.      
     
     
       54. The method of  claim 53  wherein said active circuit is an electrostatic discharge unit.  
     
     
       55. The method of  claim 53  wherein said active circuit comprises a circuit selected from the group consisting of: a transistor, a resistor, a capacitor, an inductor, or any combination thereof.  
     
     
       56. The method of  claim 53  wherein forming said array of openings in said uppermost metal layer forms a conductive region taking the shape of a waffle.  
     
     
       57. The method of  claim 53  wherein said dielectric layer comprises of silicon dioxide.  
     
     
       58. The method of  claim 57  wherein forming said array of openings in said uppermost metal layer forms a conductive region taking the shape of a grid.  
     
     
       59. The method of  claim 53  wherein said uppermost metal layer is formed from a material selected from the group consisting of: polysilicon, silicon alloys, aluminum, aluminum alloys, gold, gold alloys, copper, and copper alloys, or any combination thereof.  
     
     
       60. The method of  claim 53  wherein said active circuit is formed on a substrate.  
     
     
       61. The method of  claim 60  wherein forming said array of openings in said uppermost metal layer forms a conductive region having rows and columns of openings.