Method for sharing configuration data for high logic density on chip

Abstract

A system for reducing the number of programmable architecture elements in a look-up table required for implementing Boolean functions or operations that are identical or logically equivalent is provided. The system may include a single set of storage elements connected to the inputs of multiple decoders, and the storage elements may be concurrently accessed by the decoders to provide simultaneous multiple outputs thereto.

1. A look-up table comprising:
 a plurality of decoders each having a plurality of inputs and an output and each having a plurality of selection lines;  
 a plurality of common storage elements connected to the inputs of said decoders;  
 a plurality of buffers respectively connected between said common storage elements and at least one of said decoders for driving the inputs of said at least one decoder; and  
 a programmable switch network selectively connecting said common storage elements to the inputs of said decoders;  
 said common storage elements being concurrently accessible by said decoders to simultaneously provide multiple outputs thereto.  
 
     
     
       2. The look-up table of  claim 1  further comprising a controllable inverter connected to the output of at least one of said decoders. 
     
     
       3. The look-up table of  claim 2  wherein said controllable inverter has a static control. 
     
     
       4. The look-up table of  claim 2  wherein said controllable inverter has a dynamic control. 
     
     
       5. The look-up table of  claim 1  further comprising an exclusive OR gate connected to the output of at least one of said decoders. 
     
     
       6. A look-up table comprising:
 a plurality of common static random access memory (SRAM) storage elements;  
 a plurality of decoders each having a plurality of inputs and an output, and each having a plurality of selection lines;  
 a plurality of buffers respectively connected between said SRAM storage elements and at least one of said decoders for driving the inputs of said at least one decoder; and  
 a programmable switch network selectively connecting said common SRAM storage elements to the inputs of said decoders;  
 said common storage elements being concurrently accessible by said decoders to simultaneously provide multiple outputs thereto.  
 
     
     
       7. The look-up table of  claim 6  further comprising a controllable inverter connected to the output of at least one of said decoders. 
     
     
       8. The look-up table of  claim 7  wherein said controllable inverter has a static control. 
     
     
       9. The look-up table of  claim 7  wherein said controllable inverter has a dynamic control. 
     
     
       10. The look-up table of  claim 6  further comprising an exclusive OR gate connected to the output of at least one of said decoders. 
     
     
       11. A method for reducing the number of programmable architecture elements in a lookup table required for implementing Boolean functions or other operations that are identical or logically equivalent, the look-up table comprising a plurality of decoders each having a plurality of inputs and an output, and each having a plurality of selection lines, the method comprising:
 connecting a plurality of common storage elements to the inputs of said decoders using a programmable switch network;  
 connecting a buffer between each of the common storage elements and at least one of the decoders for driving the inputs of the at least one decoder; and  
 using the decoders to concurrently accesses the common storage elements to simultaneously receive multiple outputs therefrom.  
 
     
     
       12. The method of  claim 11  further comprising inverting the output of at least one of the decoders. 
     
     
       13. The method of  claim 12  wherein inverting comprises performing statically controlled inversion. 
     
     
       14. The method of  claim 12  wherein inverting comprises performing dynamically controlled inversion. 
     
     
       15. A method for performing logical operations comprising:
 providing a look-up table comprising a plurality of decoders each having a plurality of inputs and an output, and each having a plurality of selection lines, a plurality of common storage elements connected to the inputs of the decoders, a plurality of buffers connected between the common storage elements and at least one of the decoders for driving the inputs of the at least one decoder, and a programmable switch network connected between the common storage elements and the inputs of the decoders;  
 selectively connecting the common storage elements to the inputs of the decoders using the programmable switch network; and  
 using the decoders to concurrently access the common storage elements to simultaneously receive multiple outputs therefrom, the decoders thereby cooperating with the storage elements to perform the logical operations.  
 
     
     
       16. The method of  claim 15  further comprising inverting the output of at least one of the decoders. 
     
     
       17. Programmable logic device circuitry comprising:
   a plurality of storage elements;        a plurality of decoders operably associated with the plurality of storage elements;        means for providing identical configuration bits to individual decoders; and        means for using the identical configuration bits to implement functions that are identical or logically equivalent.     
     
     
       18. The programmable logic device circuitry of  claim 17 , wherein the means for using comprises one or more controlled inverters operably connected to one or more of the plurality of decoders. 
     
     
       19. The programmable logic device circuitry of  claim 18 , wherein the one or more controlled inverters have static controls. 
     
     
       20. The programmable logic device circuitry of  claim 18 , wherein the one or more controlled inverters have dynamic controls. 
     
     
       21. The programmable logic device circuitry of  claim 17 , wherein the means for using comprises one or more controlled inverters operably connected to one or more select lines of one or more of the plurality of decoders. 
     
     
       22. The programmable logic device circuitry of  claim 21 , wherein the one or more controlled inverters have static controls. 
     
     
       23. The programmable logic device circuitry of  claim 21 , wherein the one or more controlled inverters have dynamic controls. 
     
     
       24. The programmable logic device circuitry of  claim 17 , wherein the means for using comprises one or more controlled inverters operably connected to an output of one or more of the plurality of decoders. 
     
     
       25. The programmable logic device circuitry of  claim 24 , wherein the one or more controlled inverters have static controls. 
     
     
       26. The programmable logic device circuitry of  claim 24 , wherein the one or more controlled inverters have dynamic controls. 
     
     
       27. The programmable logic device circuitry of  claim 17 , wherein the means for using comprises:
   one or more controlled inverters operably connected to one or more select lines of one or more of the plurality of decoders; and        one or more other controlled inverters operably connected to an output of one or more of the plurality of decoders.     
     
     
       28. The programmable logic device circuitry of  claim 27 , wherein at least some of the controlled inverters have static controls. 
     
     
       29. The programmable logic device circuitry of  claim 27 , wherein at least some of the controlled inverters have dynamic controls. 
     
     
       30. The programmable logic device circuitry of  claim 17 , wherein the functions comprise at least  4 - variable functions.   
     
     
       31. The programmable logic device circuitry of  claim 30 , wherein  4 - variable functions comprise parent functions, and wherein at least some children functions of the parent functions have lesser numbers of variables.   
     
     
       32. Programmable logic device circuitry comprising:
   a plurality of storage elements;        a plurality of decoders operably associated with the plurality of storage elements;        first circuitry configured to provide identical configuration bits to individual decoders; and        second circuitry configured to use the identical configuration bits to implement Boolean functions that are identical or logically equivalent.     
     
     
       33. The programmable logic device circuitry of  claim 32 , wherein the second circuitry comprises one or more controlled inverters operably connected to one or more of the plurality of decoders. 
     
     
       34. The programmable logic device circuitry of  claim 32 , wherein the second circuitry comprises one or more controlled inverters operably connected to one or more select lines of one or more of the plurality of decoders. 
     
     
       35. The programmable logic device circuitry of  claim 32 , wherein the second circuitry comprises one or more controlled inverters operably connected to an output of one or more of the plurality of decoders. 
     
     
       36. The programmable logic device circuitry of  claim 32 , wherein the second circuitry comprises:
   one or more controlled inverters operably connected to one or more select lines of one or more of the plurality of decoders; and        one or more other controlled inverters operably connected to an output of one or more of the plurality of decoders.     
     
     
       37. The programmable logic device circuitry of  claim 32 , wherein the functions comprise at least  4 - variable functions.   
     
     
       38. The programmable logic device circuitry of  claim 37 , wherein  4 - variable functions comprise parent functions, and wherein at least some children functions of the parent functions have lesser numbers of variables.   
     
     
       39. A method comprising:
   accessing, using multiple decoders in a programmable logic device, common storage elements to receive multiple outputs from the common storage elements; and        operating the multiple decoders, using the multiple outputs, to implement functions or other operations that are identical or logically equivalent.     
     
     
       40. The method of  claim 39 , wherein said operating comprises inverting one or more inputs to one or more of the multiple decoders. 
     
     
       41. The method of  claim 39 , wherein said operating comprises inverting one or more outputs of one or more of the multiple decoders. 
     
     
       42. The method of  claim 39 , wherein said operating comprises:
   inverting one or more inputs to one or more of the multiple decoders; and        inverting one or more outputs of the one or more multiple decoders.     
     
     
       43. The method of  claim 39 , wherein said functions comprise Boolean functions. 
     
     
       44. The method of  claim 39 , wherein said common storage elements comprise SRAM latches. 
     
     
       45. The method of  claim 39 , wherein said functions comprise at least  4 - variable functions.   
     
     
       46. The method of  claim 45 , wherein  4 - variable functions comprise parent functions, and wherein at least some children functions of the parent functions have lesser numbers of variables.   
     
     
       47. A method comprising:
   buffering inputs to at least one decoder of a collection of decoders in a programmable logic device, said inputs being received from common storage elements; and        concurrently accessing, with the collection of decoders, the common storage elements effective to implement functions or other operations that are identical or logically equivalent.     
     
     
       48. The method of  claim 47  further comprising inverting at least one select line to at least one of the decoders. 
     
     
       49. The method of  claim 47  further comprising inverting at least one output of at least one of the decoders. 
     
     
       50. The method of  claim 47  further comprising:
   inverting at least one select line to at least one of the decoders; and        inverting at least one output of at least one of the decoders.     
     
     
       51. The method of  claim 47 , wherein said functions comprise Boolean functions. 
     
     
       52. The method of  claim 47 , wherein said common storage elements comprises SRAM latches. 
     
     
       53. The method of  claim 47 , wherein the functions comprise at least  4 - variable functions.   
     
     
       54. The method of  claim 53 , wherein  4 - variable functions comprise parent functions, and wherein at least some children functions of the parent functions have lesser numbers of variables.