Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device is comprised of a semiconductor element having a low dielectric constant insulating film, first electrode pads and barrier metal layers; and a substrate having second electrode pads corresponding to the first electrode pads. The first electrode pads and the second electrode pads are connected via metal bumps. The barrier metal layers having a thickness in a range of 0.1 to 3 μm are interposed between the metal bumps and the first electrode pads. Besides, when it is assumed that the barrier metal layers have a diameter D 1 , the second electrode pads have an opening diameter D 2 and the metal bumps have a minimum pitch p, the diameter D 1 of the barrier metal layers satisfies at least one of conditions of D 1 ≧D 2 and D 1 =0.4 p to 0.7 p. Thus, the occurrence of a crack, peeling or the like due to the low dielectric constant insulating films can be retarded.

1. A semiconductor device, comprising:
 a semiconductor element having an element body that comprises (i) a low dielectric constant insulating film having a specific inductive capacity of 3.5 or less and (ii) conductor wires embedded in the low dielectric constant insulating film, first electrode pads disposed on the conductor wires of the element body, and barrier metal layers formed on the first electrode pads and having a thickness in a range of 0.1 to 3 μm;  
 metal bumps connected to the first electrode pads via the barrier metal layers; and  
 a substrate having second electrode pads which are connected to the first electrode pads via the metal bumps.  
 
     
     
       2. The semiconductor device according to  claim 1 , wherein a diameter D 1  of the barrier metal layers and an opening diameter D 2  of the second electrode pads satisfy a relationship of D 1 >D 2 . 
     
     
       3. The semiconductor device according to  claim 1 , wherein a diameter D 1  of the barrier metal layers and a minimum pitch p of the metal bumps satisfy a relationship of D 1 =0.4 p to 0.7 p. 
     
     
       4. The semiconductor device according to  claim 1 , wherein a diameter D 1  of the barrier metal layers, an opening diameter D 2  of the second electrode pads and a minimum pitch p of the metal bumps satisfy relationships of D 1 >D 2  and D 1 =0.4 p to 0.7 p. 
     
     
       5. The semiconductor device according to  claim 1 , wherein the metal bumps are formed of a nonlead solder material substantially not containing lead. 
     
     
       6. A semiconductor device, comprising:
 a semiconductor element having an element body that comprises (i) a low dielectric constant insulating film having a specific inductive capacity of 3.5 or less and (ii) conductor wires embedded in the low dielectric constant insulating film, first electrode pads disposed on the conductor wires of the element body, and barrier metal layers formed on the first electrode pads and having a diameter D 1 ;  
 metal bumps connected to the first electrode pads via the barrier metal layers; and  
 a substrate having second electrode pads which are connected to the first electrode pads via the metal bumps and have an opening diameter D 2 ,  
 wherein the diameter D 1  satisfies a relationship of D 1 >D 2 .  
 
     
     
       7. The semiconductor device according to  claim 6 , wherein the second electrode pads have the opening diameter D 2  satisfying a relationship of 0.5D 1 ≦D 2 ≦0.9D 1 . 
     
     
       8. The semiconductor device according to  claim 6 , wherein a minimum pitch p of the metal bumps satisfies a relationship of D 1 =0.4 p to 0.7 p. 
     
     
       9. The semiconductor device according to  claim 6 , wherein the metal bumps are formed of a nonlead solder material substantially not containing lead. 
     
     
       10. A semiconductor device, comprising:
 a semiconductor element having an element body that comprises (i) a low dielectric constant insulating film having a specific inductive capacity of 3.5 or less and (ii) conductor wires embedded in the low dielectric constant insulating film, first electrode pads disposed on the conductor wires of the element body, and barrier metal layers formed on the first electrode pads and having a diameter D 1 ;  
 metal bumps connected to the first electrode pads via the barrier metal layers, and having a minimum pitch p; and  
 a substrate having second electrode pads which are connected to the first electrode pads via the metal bumps,  
 wherein the diameter D 1  satisfies a relationship of D 1 =0.4 p to 0.7 p.  
 
     
     
       11. The semiconductor device according to  claim 10 , wherein the metal bumps are formed of a nonlead solder material substantially not containing lead. 
     
     
       12. A semiconductor device, comprising:
   a first semiconductor body;        a low - k dielectric film disposed on the first semiconductor body containing Si and C having a specific inductive capacity of  3 . 5  or less;        conductor wires disposed in the low - k dielectric film;        first electrode pads respectively connected to the conductor wires;        a barrier metal layer having a thickness in the range of  0 . 3  to  2  μm comprised of a material selected from the group of Ta, Ti, TaN, TiN disposed on each of the first electrode pads; and        metal bumps electrically connected to the barrier metal layers, respectively.     
     
     
       13. The semiconductor device according to  claim 12 , wherein a width of the barrier metal layer is in the range of  0 . 4  to  0 . 7  times a minimum pitch of the metal bumps. 
     
     
       14. The semiconductor device according to  claim 13 , wherein a width of the barrier metal layer is in the range of  0 . 55  to  0 . 65  times a minimum pitch of the metal bumps. 
     
     
       15. The semiconductor device according to  claim 12 , wherein the low- k dielectric film comprises two or more stacked layers, each containing Si and C.   
     
     
       16. The semiconductor device according to  claim 12 , comprising the low- k dielectric film having an adhesion strength to one of the first semiconductor body and a metal film of no more than  15  J/m   2   .   
     
     
       17. The semiconductor device according to  claim 12 , comprising:
   a second body having second electrode pads electrically connected to the metal bumps, respectively.     
     
     
       18. The semiconductor device according to  claim 17 , comprising:
   a width of the barrier metal layer being equal to or larger than a width of the second electrode pad.     
     
     
       19. The semiconductor device according to  claim 18 , wherein a width of the barrier metal layer is in the range of  0 . 4  to  0 . 7  times a minimum pitch of the metal bumps. 
     
     
       20. The semiconductor device according to  claim 19 , wherein a width of the barrier metal layer is in the range of  0 . 55  to  0 . 65  times a minimum pitch of the metal bumps. 
     
     
       21. The semiconductor device according to  claim 12 , comprising the barrier metal layer having a circular shape. 
     
     
       22. The semiconductor device according to  claim 21 , comprising:
   a diameter of the barrier metal layer being equal to or larger than a diameter of the second electrode pad.     
     
     
       23. The semiconductor device according to  claim 22 , wherein a diameter of the barrier metal layer is in the range of  0 . 4  to  0 . 7  times a minimum pitch of the metal bumps. 
     
     
       24. The semiconductor device according to  claim 23 , wherein a diameter of the barrier metal layer is in the range of  0 . 55  to  0 . 65  times a minimum pitch of the metal bumps. 
     
     
       25. The semiconductor device according to  claim 22 , wherein the barrier metal layer is Ti. 
     
     
       26. A semiconductor device, comprising:
   a semiconductor element having an element body that comprises a low dielectric constant insulating film having a specific inductive capacity of  3 . 5  or less and conductor wires embedded in the low dielectric constant insulating film;        first electrode pads disposed on the conductor wires;        barrier metal layers formed on the first electrode pads and having a thickness in a range of  0 . 1  to  3  μm;        metal bumps composed of a Pb/Sn material connected to the first electrode pads via the barrier metal layers; and        a substrate having second electrode pads formed of a Cu material which are connected to the first electrode pads via the metal bumps,        the Cu material directly contacting the Pb/Sn material, and        a material of the metal bump contacting the second electrode pad is primarily composed of Sn.     
     
     
       27. The semiconductor device according to  claim 26 , wherein the barrier metal layers have a thickness in a range of  0 . 3  to  2  μm. 
     
     
       28. The semiconductor device according to  claim 26 , wherein the low dielectric constant insulating film comprises two or more stacked layers each containing Si and C. 
     
     
       29. The semiconductor device according to  claim 26 , wherein the first electrode pads include an Al layer, and the barrier metal layers are disposed on the Al layer. 
     
     
       30. The semiconductor device according to  claim 26 , wherein a width of the barrier metal layer is in the range of  0 . 4  to  0 . 7  times a minimum pitch of the metal bumps. 
     
     
       31. The semiconductor device according to  claim 30 , wherein a width of the barrier metal layer is in the range of  0 . 55  to  0 . 65  times a minimum pitch of the metal bumps. 
     
     
       32. A semiconductor device, comprising:
   a semiconductor element having an element body that comprises a low dielectric constant insulating film having a specific inductive capacity of  3 . 5  or less and conductor wires embedded in the low dielectric constant insulating film;        first electrode pads disposed on the conductor wires; and        barrier metal layers formed on the first electrode pads and having a thickness in a range of  0 . 1  to  3  μm;        metal bumps primarily composed of a Sn material connected to the first electrode pads via the barrier metal layers; and        a substrate having second electrode pads composed of a Cu material which are physically connected to the metal bumps.     
     
     
       33. The semiconductor device according to  claim 32 , wherein the barrier metal layers have a thickness in a range of  0 . 3  to  2  μm. 
     
     
       34. The semiconductor device according to  claim 32 , wherein the low dielectric constant insulating film comprises two or more stacked layers each containing Si and C. 
     
     
       35. The semiconductor device according to  claim 32 , wherein the first electrode pads include an Al layer, and the barrier metal layers are disposed on the Al layer. 
     
     
       36. The semiconductor device according to  claim 32 , wherein a width of the barrier metal layer is in the range of  0 . 4  to  0 . 7  times a minimum pitch of the metal bumps. 
     
     
       37. The semiconductor device according to  claim 36 , wherein a width of the barrier metal layer is in the range of  0 . 55  to  0 . 65  times a minimum pitch of the metal bumps.