Deep wordline trench to shield cross coupling between adjacent cells for scaled NAND

Abstract

A NAND flash memory structure with a wordline or control gate that provides shielding from Yupin effect errors and generally from potentials in adjacent strings undergoing programming operations with significant variations in potential.

1. A multi-state flash memory device formed from a substrate in which individual memory cells can store multiple bits represented as charges of more than two possible levels, the device comprising:
 a plurality of strings of transistors of a NAND architecture, each string of the plurality of strings comprising a first select gate, a plurality of floating gates, and a second select gate, the plurality of floating gates formed above channel regions in the substrate and separated from the channel regions, 
 wherein a controller circuit is adapted to cause adjacent first and second strings of the plurality of strings to undergo programming operations at the same time, the programming operations including setting different voltages levels in floating gates of the adjacent first and second strings, and 
 wherein when the plurality of strings of transistors is arranged such that, during programming of a selected floating gate of the first string, a change in a potential of a portion of the second adjacent string is shielded from the selected floating gate of the first string by a wordline extending across adjacent strings and extending between floating gates of the first and second strings into a shallow trench isolation trench between the channel regions of the first and second strings. 
 
     
     
       2. The flash memory device of  claim 1  wherein the wordline shields the selected floating gate of the first string from a potential in the substrate at the second string. 
     
     
       3. The flash memory device of  claim 1  wherein the wordline shields the selected floating gate of the first string from a potential of the adjacent floating gate of the second string. 
     
     
       4. The flash memory device of  claim 1  further comprising a gate oxide layer between the floating gates and the substrate, the wordline extending down past the level of an upper surface of the gate oxide layer. 
     
     
       5. The flash memory device of  claim 1  wherein the wordline shields the selected floating gate of the first string from the potential of a floating gate of the second adjacent string. 
     
     
       6. A flash memory device comprising:
 a plurality of strings of adjacent transistors of a NAND architecture, individual strings of the plurality of strings comprising a first select gate, a plurality of floating gates, and a second select gate, the plurality of floating gates formed above a substrate; 
 shallow trench isolation trenches between adjacent ones of the plurality of strings; 
 wordlines extending across the plurality of strings and extending between floating gates into the shallow trench isolation trenches between adjacent strings of the plurality of strings, 
 wherein in the case of programming adjacent strings of the plurality of NAND strings, a channel of a first string adjacent a floating gate of a second string is at a first potential for a number of programming pulses and is at a second potential during subsequent programming pulses, 
 wherein the potential of the channel of the first string couples to the potential of the floating gate of the second string, and 
 wherein the wordline shields the floating gate of the second string from the potential of the channel of the first string thereby affecting the coupling to the potential of the floating gate. 
 
     
     
       7. The flash memory device of  claim 6  further comprising a gate oxide layer between the floating gates and the substrate, the wordlines extending down past the level of an upper surface of the gate oxide layer. 
     
     
       8. The flash memory device of  claim 6  wherein the wordlines extend down past the level of an upper surface of the substrate. 
     
     
       9. The flash memory device of  claim 6  wherein the wordlines extend down past the lower level of the channel. 
     
     
       10. A flash memory device formed from a substrate, the device comprising:
 a plurality of strings of transistors of a NAND architecture, each string of the plurality of strings comprising a first select gate, a plurality of floating gates, and a second select gate, the plurality of floating gates formed above the substrate, a plurality of control gates, each control gate of the plurality of control gate overlying a floating gate; 
 the plurality of floating gates formed above a gate oxide layer formed upon cell channel regions within the substrate; and 
 a plurality of wordlines that extend across the plurality of strings to connect control gates of different strings and that extend between the floating gates of adjacent strings, each wordline of the plurality of wordlines extending down past an upper surface of the substrate to shield a selected floating gate during a read or verify operation from a potential present in an adjacent string. 
 
     
     
       11. The flash memory device of  claim 10  wherein a wordline of the plurality of wordlines shields the selected floating gate from the potential of the substrate beneath the adjacent string. 
     
     
       12. The flash memory device of  claim 11  wherein a wordline of the plurality of wordlines shields the selected floating gate from the potential of a channel region of the substrate beneath the adjacent string. 
     
     
       13. The flash memory device of  claim 10  wherein a wordline of the plurality of wordlines shields the selected floating gate from a potential of a floating gate of the adjacent string. 
     
     
       14. A multi-state flash memory device formed from a substrate in which individual memory cells can store multiple bits represented as charges of more than two possible levels, the device comprising:
 a plurality of strings of transistors of a NAND architecture arranged longitudinally in the memory device, each string of the plurality of strings comprising a first select gate, a plurality of floating gates, and a second select gate, the plurality of floating gates formed above channel regions in the substrate and separated from the channel regions;   wherein a controller circuit is adapted to cause adjacent first and second strings of the plurality of strings to undergo programming operations at the same time, the programming operations including setting different voltages levels in floating gates of the adjacent first and second strings, and   structure in the NAND architecture that at least partially shields a change in a potential of a portion of one adjacent string from a selected floating gate of another adjacent string when the other adjacent string is programmed by a wordline situated transversely over adjacent strings and including shielding portions extending towards the substrate between floating gates of the first and second strings.   
     
     
       15. The flash memory device of claim 14 wherein the wordline shields the selected floating gate of the other adjacent string from the potential of a floating gate of the one adjacent string. 
     
     
       16. A multi-state flash memory device formed from a substrate in which individual memory cells can store multiple bits represented as charges of more than two possible levels, the device comprising:
 a plurality of strings of transistors of a NAND architecture arranged longitudinally in the memory device, each string of the plurality of strings comprising a first select gate, a plurality of floating gates, and a second select gate, the plurality of floating gates formed above the substrate, a plurality of control gates, each control gate of the plurality of control gate overlying a floating gate, the plurality of floating gates formed above a gate oxide layer formed upon cell channel regions within the substrate;   wherein a controller circuit is adapted to cause adjacent first and second strings of the plurality of strings to undergo programming operations at the same time, the programming operations including setting different voltages levels in floating gates of the adjacent first and second strings, and   a plurality of wordlines situated transversely over the plurality of strings to connect control gates of different strings and that include shielding portions extending towards the substrate between the floating gates of adjacent strings, to shield a selected floating gate during a read or verify operation from a potential present in an adjacent string.   
     
     
       17. The flash memory device of claim 16 wherein a wordline of the plurality of wordlines shields the selected floating gate from a potential of a floating gate of the adjacent string. 
     
     
       18. In manufacturing a memory device to have a plurality of memory cells having floating gates in which a programmable charge from among more than two levels is to be stored such that individual memory cells can represent multiple bits, the plurality of memory cells arranged over a substrate to form columns along a longitudinal direction and rows along a transverse direction, the memory electrically arranged such that bit lines corresponding to the columns are situated along the longitudinal direction, and word lines corresponding to the rows are arranged over the memory cells along the transverse direction, a method of shielding memory cells from one another, the method comprising:
 arranging the plurality of word lines in rows along the transverse direction over corresponding rows of the memory cells such that each of the word lines is capacitively coupled with memory cells of a corresponding row;   providing a controller circuit that is adapted to cause adjacent first and second strings of the plurality of strings to undergo programming operations at the same time, the programming operations including setting different voltages levels in floating gates of the adjacent first and second strings, and   forming the plurality of word lines such that each word line includes a set of shielding portions extending towards the substrate between adjacent memory cells of the row of memory cells corresponding to that word line, thereby causing the word lines to at least partially shield the adjacent memory cells from one another.   
     
     
       19. A flash memory device comprising:
 strings of adjacent transistors of a NAND architecture comprising a first select gate, a plurality of floating gates, and a second select gate, the plurality of floating gates formed above a substrate, with a channel of a first string adjacent a floating gate of a second string at a first potential for a number of programming pulses and at a second, different potential for a subsequent number of programming pulses; and   means for controlling the floating gates to be programmed at the same time to different levels and for shielding the floating gates from variations of adjacent potential fields during and between program pulses, the means for controlling the floating gates and for shielding the floating gates being situated over the floating gates and extending toward the substrate between the floating gates.   
     
     
       20. In a memory having a plurality of strings of memory cells arranged to form columns across a substrate surface and individually including a floating gate, wherein the strings of memory cells are separated by dielectric between them, and wherein a plurality of word lines extend across rows of memory cell floating gates the dielectric therebetween, a method of programming charge levels on an individual row of memory cells to defined states, comprising:
 alternatively applying program pulses to and reading the states of memory cells along the row,   in response to reading that a memory cell along the row has reached its defined state, ceasing to apply any further programming pulses to such a memory cell while continuing to apply programming pulses to other memory cells in the row until all of the memory cells along the row have reached their defined states, and   utilizing shielding between the floating gates in the row during the alternate application of program pulses to and reading the state of the memory cells along the row by maintaining portions of the word lines between adjacent floating gates and extending toward the dielectric therebetween.   
     
     
       21. The method of claim 20, wherein in using the shielding, the dielectric fills trenches formed into the substrate surface between the strings of memory cells. 
     
     
       22. The method of claim 21, wherein providing shielding includes maintaining the word lines below the level of the substrate surface. 
     
     
       23. The method of claim 22, wherein applying program pulses includes applying programming pulses that are successively increased in magnitude.