Printed wiring board and method for manufacturing the same

Abstract

A printed circuit board is by formed by laminating an interlaminar insulating layer on a conductor circuit of a substrate, in which the conductor circuit is comprised of an electroless plated film and an electrolytic plated film and a roughened layer is formed on at least a part of the surface of the conductor circuit.

1. A multilayer printed circuit board comprising a plurality of interlaminar insulating layers and conductor circuits, said printed circuit board being formed by laminating a first interlaminar insulating layer on a conductor circuit of a substrate and forming at least a second conductor circuit and a second interlaminar insulating layer on the first interlaminar insulating layer, wherein
 at least a part of the surface of the interlaminar insulating layers is a roughened surface, 
 the conductor circuits are comprised of an electroless plated film formed on an interlaminar insulating layer and an electrolytic plated film formed on the electroless plated film, said electroless plated film having a thickness ranging from 0.1 μm to 5 μm and configured to follow the roughened surface of the interlaminar insulating layer, and 
 a roughened layerat least a part of the surface of the conductor circuits is a roughened surface formed by a roughening treatment on at least a part of the surface of the conductor circuits. 
 
     
     
       2. A printed circuit board according to clam  1 , wherein the roughened layer surface of the conductor circuit is on at least a part of the surface inclusive of a side surface of the conductor circuit thereof. 
     
     
       3. A printed circuit board according to  claim 1 , wherein the roughened layer surface of the conductor circuit is on at least a part of a side face of the conductor circuit thereof. 
     
     
       4. A printed circuit board according to  claim 1 , wherein the roughened layer is surface of the conductor circuit comprises a plated layer of copper-nickel-phosphorus alloy. 
     
     
       5. The printed circuit board according to  claim 1 , wherein the electrolytic plated film is formed on the electroless plated film. 
     
     
       6. A printed circuit board according to  claim 1 , wherein the roughening treatment comprises is one of an etching treatment, polishing treatment, redox treatment, or and plating treatment. 
     
     
       7. A printed circuit board according to  claim 1 , wherein the electroless plated film comprises an inner layer side and the electrolytic plated film comprises an outer layer side and the roughened layer surface of the conductor circuit is formed on the electrolytic plated film. 
     
     
       8. A printed circuit board according to  claim 2 , wherein the roughened layer is surface of the conductor circuit comprises a plated layer of copper-nickel-phosphorus alloy. 
     
     
       9. A printed circuit board according to  claim 3 , wherein the roughened layer is surface of the conductor circuit comprises a plated layer of copper-nickel-phosphorus alloy. 
     
     
       10. A multilayer printed circuit board comprising a plurality of interlaminar insulating layers and conductor circuits, said printed circuit board being formed by laminating a first interlaminar insulating layer on a conductor circuit of a substrate and forming at least a second conductor circuit and a second interlaminar insulating layer on the first interlaminar insulating layer, wherein the conductor circuits are comprised of an electroless plated film and an electrolytic plated film, and a roughened layer formed by a roughening treatment on at least a part of the surface of the conductor circuits, and the surface of the roughened layer according to claim 1, wherein the roughened surface of the conductor circuit is covered with a layer of a metal having an ionization tendency of more than copper but not higher than titanium, or of a noble metal. 
     
     
       11. A printed circuit board according to  claim 10 , wherein the roughened layer surface of the conductor circuit is on at least a part of the surface inclusive of a side surface of the conductor circuit thereof. 
     
     
       12. A printed circuit board according to  claim 10 , wherein the roughened layer surface of the conductor circuit is on at least a part of a side face of the conductor circuit thereof. 
     
     
       13. A painted printed circuit board according to  claim 10 , wherein the roughened layer is surface of the conductor circuit comprises a plated layer of copper-nickel-phosphorus alloy. 
     
     
       14. The printed circuit board according to  claim 10 , wherein the electrolytic plated film is formed on the electroless plated film. 
     
     
       15. A printed circuit board according to  claim 10 , wherein the roughening treatment comprises is one of an etching treatment, polishing treatment, redox treatment, or and plating treatment. 
     
     
       16. A printed circuit board according to  claim 10 , wherein the electroless plated film comprises an inner layer side and the electrolytic plated film comprises an outer layer side and the roughened layer surface of the conductor circuit is formed on the electrolytic plated film. 
     
     
       17. A multilayer printed circuit board comprising a substrate provided with an under layer conductor circuit, an interlaminar insulating layer formed thereon and an upper layer conductor circuit formed on the interlaminar insulating layer, and a viahole connecting both the conductor circuits to each other, in which at least a part of the surface of the interlaminar insulating layer is a roughened surface, the viahole is comprised of an electroless plated film formed on the interlaminar insulating layer and an electrolytic plated film formed on the electroless plated film having a thickness ranging from 0.1 μm to 5 μm and configured to follow the roughened surface of the interlaminar insulating layer, and a roughened layer on at least a part of the surface of the under layer conductor circuit connected electrically to the viahole, said roughened layer having a roughened surface formed by etching treatment, polishing treatment, redox treatment or plating treatment a roughening treatment. 
     
     
       18. A multilayer printed circuit board according to  claim 17 , wherein the roughened layer is formed by plating surface of the conductor circuit comprises a plated layer of copper-nickel-phosphorus alloy. 
     
     
       19. The printed circuit board according to  claim 17 , wherein the electrolytic film is formed on the electroless plated film. 
     
     
       20. A printed circuit board according to  claim 17 , wherein the electroless plated film comprises an inner layer side and the electrolytic plated film comprises an outer layer side and the roughened layer surface of the conductor circuit is formed on the electrolytic plated film. 
     
     
       21. A method of producing a multilayer printed circuit board comprising subjecting a surface of a substrate forming a first interlaminar insulating layer on a surface of a substrate, at least one conductor circuit being provided on the surface of the substrate, roughening at least a part of the surface of the first interlaminar insulating layer to form a roughened surface, subjecting the first interlaminar insulating layer to an electroless plating to form an electroless plated film having a thickness ranging from 0.1 μm to 5 μm, forming a plating resist thereon, subjecting the substrate first interlaminar insulating layer to an electrolytic plating, removing the plating resist, etching and removing the electroless plated film beneath the plating resist to form a at least one second conductor circuit comprised of the electroless plated film and the electrolytic plated film formed on the electroless plated film, forming a roughened layer on roughening at least a part of the surface of the second conductor circuit to form a roughened surface and then forming an a second interlaminar insulating layer on the second conductor circuit. 
     
     
       22. A method of producing a printed circuit board according to  claim 21 , wherein the roughened layer surface of the second conductor circuit is formed by plating of copper-nickel-phosphorus alloy. 
     
     
       23. The method according to  claim 21 , wherein the electrolytic film is formed on the electroless plated film. 
     
     
       24. A method of producing a multilayer printed circuit board according to claim 21, further comprising subjecting a surface of a substrate to an electroless plating, forming a plating resist thereon, subjecting the substrate to an electrolytic plating, removing the plating resist, etching and removing the electroless plated film beneath the plating resist to form a conductor circuit comprised of the electroless plated film and the electrolytic plated film, forming a roughened layer on at least a part of the surface of the conductor circuit, covering the surface of the roughened layer roughened surface of the second conductor circuit with a layer of a metal having an ionization tendency of more than copper but not higher than titanium, or of a noble metal, and forming an interlaminar insulating layer before forming the second interlaminar insulating layer. 
     
     
       25. A method of producing a printed circuit board according to  claim 24 , wherein the roughened layer surface of the second conductor circuit is formed by plating of copper-nickel-phosphorus alloy. 
     
     
       26. The method according to  claim 24 , wherein the electrolytic film is formed on the electroless plated film. 
     
     
       27. A method of producing a multilayer printed circuit board comprising forming a at least one lower conductor circuit layer on a surface of a substrate, forming a roughened layer by etching treatment, polishing treatment, redox treatment, or plating treatment on roughening at least a part of the surface of the underlayer lower conductor circuit connected to a viahole by a roughening treatment, forming an interlaminar insulating layer thereon, forming openings for viaholes in the interlaminar insulating layer, roughening at least a part of the interlaminar insulating layer to form a roughened surface, subjecting the interlaminar insulating layer to an electroless plating to form an electroless plated film having a thickness ranging from 0.1 μm to 5 μm, forming a plating resist thereon, subjecting the interlaminar insulating layer to an electrolytic plating, removing the plating resist, etching and removing the electroless plated film beneath the plating resist to form an upper layer at least one upper conductor circuit comprised of the electroless plated film and the electrolytic plated film formed on the electroless plated film and a at least one viahole connecting the lower conductor circuit and the upper conductor circuit. 
     
     
       28. A method of producing a multilayer printed circuit board according to  claim 27 , wherein the roughened layer surface of the lower conductor circuit is formed by plating of copper-nickel-phosphorus alloy. 
     
     
       29. The method according to  claim 27 , wherein the electrolytic film is formed on the electroless plated film. 
     
     
       30. A printed circuit board according to claim 1, wherein the electrolytic plated film has a thickness of 5 to 30 μm. 
     
     
       31. A printed circuit board according to claim 10, wherein the electrolytic plated film has a thickness of 5 to 30 μm. 
     
     
       32. A printed circuit board according to claim 17, wherein the electrolytic plated film has a thickness of 5 to 30 μm. 
     
     
       33. A printed circuit board according to claim 17, wherein the roughening treatment is one of an etching treatment, polishing treatment, redox treatment, and plating treatment. 
     
     
       34. A method of producing a multilayer printed circuit board according to claim 21, wherein the electrolytic plated film has a thickness of 5 to 30 μm. 
     
     
       35. A method of producing a multilayer printed circuit board according to claim 21, further comprising roughening at least a part of the surface of the first interlaminar insulating layer, forming at least one opening portion for a viahole connecting the conductor circuit of the substrate with the second conductor circuit in the first interlaminar insulating layer by a laser method. 
     
     
       36. A method of producing a multilayer printed circuit board according to claim 21, wherein the electroless plated film follows the roughened surface of the first interlaminar insulating layer. 
     
     
       37. A method of producing a multilayer printed circuit board according to claim 21, wherein the roughening treatment is one of an etching treatment, polishing treatment, redox treatment, and plating treatment. 
     
     
       38. A method of producing a multilayer printed circuit board according to claim 27, wherein the electrolytic plated film has a thickness of 5 to 30 μm. 
     
     
       39. A method of producing a multilayer printed circuit board according to claim 27, wherein the openings for the viaholes are formed by a laser method. 
     
     
       40. A method of producing a multilayer printed circuit board according to claim 27, wherein the electroless plated film follows the roughened surface of the first interlaminar insulating layer. 
     
     
       41. A method of producing a multilayer printed circuit board according to claim 27, wherein the roughening treatment is one of an etching treatment, polishing treatment, redox treatment, and plating treatment.